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Circuits, Devices & Systems, IET

Issue 1 • Date February 2009

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Displaying Results 1 - 5 of 5
  • Integrated cross-coupled chaos oscillator applied to random number generation

    Page(s): 1 - 11
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (712 KB)  

    A new cross-coupled LC chaos oscillator suitable for IC realisation is presented. The proposed circuit was fabricated using a 0.35 mum CMOS process and test results showing its feasibility are given. As a possible application, a method for using the proposed oscillator as the core of a random number generator is described. Experimental binary data obtained according to the proposed method pass the four tests of FIPS-140-2, the full NIST-800-22 and DIEHARD random number test suites. View full abstract»

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  • Field programmable gate array-based design and realisation of automatic censored cell averaging constant false alarm rate detector based on ordered data variability

    Page(s): 12 - 21
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (279 KB)  

    The design and field programmable gate array (FPGA)-based realisation of automatic censored cell averaging (ACCA) constant false alarm rate (CFAR) detector based on ordered data variability (ODV) is discussed here. The ACCA-ODV CFAR algorithm has been recently proposed in the literature for detecting radar target in non-homogeneous background environments. The ACCA-ODV detector estimates the unknown background level by dynamically selecting a suitable set of ranked cells and doing successive hypothesis tests. The proposed detector does not require any prior information about the background environment. It uses the variability index statistic as a shape parameter to accept or reject the ordered cells under investigation. Recent advances in FPGA technology and availability of sophisticated design tools have made it possible to realise the computation intensive ACCA-ODV detector in hardware, in a cost-effective way. The architecture is modular and has been implemented and tested on an Altera Stratix II FPGA using Quartus II software. The post place and route result show that the proposed design can operate at 100-MHz, the maximum clock frequency of the prototyping board and for this frequency the total processing time required to perform a single run is 0.21--s. This amounts to a speedup for the FPGA-based hardware implementation by a factor of -110 as compared to software-based implementation, which takes 23--s to perform the same operation. View full abstract»

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  • Concurrent error detection and correction in dual basis multiplier over GF(2m)

    Page(s): 22 - 40
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (441 KB)  

    Fault-based side-channel cryptanalysis is a useful technique against symmetrical and asymmetrical encryption/decryption algorithms. Thus, eliminating cryptographic computation errors become critical in preventing such kind of attacks. A simple way to eliminating cryptographic computation errors is to output correct or corrected ciphers. Multiplication is the most important finite field arithmetic operation in the cryptographic computations. By using time redundancy technique, a novel dual basis (DB) multiplier over Galois fields (2m) will be presented with lower space complexity and feedback-free property. Based on the proposed feedback-free DB multiplier, the DB multiplier with a concurrent error detection (CED) capability is also easily developed. Compared with the existing DB multiplier with CED capability, the proposed one saves about 90% of time-area complexity. No existing DB multiplier in the literature has concurrent error correction (CEC) capability. Based on the proposed DB multiplier, a novel DB multiplier with CEC capability is easily designed. The proposed DB multiplier with CEC capability requires only about 3% of extra space complexity and 15% of time complexity when compared with the proposed DB multiplier without CEC. View full abstract»

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  • New building block: multiplication-mode current conveyor

    Page(s): 41 - 48
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (899 KB)  

    A new building block called the multiplication-mode current conveyor (MMCC) is proposed here. The structure consists of a differential voltage current conveyor (DVCC) and a folded Gilbert cell without any other auxiliary circuits. Based on the MMCC, a four-quadrant analogue multiplier is designed in TSMC 0.35 mum CMOS 2P4M processes with power supply plusmn 1.65 V. HSPICE post-layout simulation results show that the maximum DC operating range is plusmn 200 mV, the loading range is from 1 to 10 kOmega, the bandwidth is about 90 MHz, the total harmonic distortion (THD) is 0.85 , the power consumption is 1.08 mW and the chip area without pads is 0.48 times 0.36 mm2. The new square summer and analogue divider applications employing MMCCs are also presented. View full abstract»

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  • Selection of the common-mode feedback network connection of fully differential Gm-C filters

    Page(s): 49 - 56
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (822 KB)  

    It is well known that fully differential (FD) structures have many advantages over their single-ended counterparts. However, the main disadvantage of FD circuit is the potential instability caused by the inherent common-mode (CM) positive feedback loop. To solve such an instability problem, extra common-mode feedback (CMFB) and/or common-mode feedforward (CMFF) circuitries are often incorporated to stabilise the circuits. We present a systematic method for checking the stability condition and identifying the most suitable CMFB network connection for a particular FD Gm-C filter. It has been demonstrated that the CMFB network connection that provides highest CM rejection is not necessarily the conventional arrangement commonly used in FD Gm-C design. View full abstract»

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Aims & Scope

IET Circuits, Devices & Systems covers circuit theory and design, circuit analysis and simulation, computer aided design,  filters, circuit implementations, cells and architectures for integration.

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