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Electron Device Letters, IEEE

Issue 11 • Date Nov. 1988

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Displaying Results 1 - 19 of 19
  • A novel CMOS VLSI isolation technology using selective chlorine implantation

    Publication Year: 1988 , Page(s): 561 - 563
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (230 KB)  

    An isolation technology that uses blanket boron and selective chlorine n-well implantation prior to field oxidation is proposed. Chlorine implantation results in an increase in the thermal-oxidation linear-reaction-rate coefficient by a factor of 11.5, which enhances the segregation of dopant atoms in the n-well field region. Due to the redistribution of dopant atoms in the n-well field region, the field threshold voltage magnitude may be increased by as much as 20 V when chlorine implantation is used.<> View full abstract»

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  • Failure in CMOS circuits induced by hot carriers in multi-gate transistors

    Publication Year: 1988 , Page(s): 564 - 566
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    The problem of vertical isolation in circuits fabricated using shallow n-well epitaxial CMOS technology is analyzed. Unexpectedly high substrate current resulting in circuit failure has been observed during accelerated reliability tests. The substrate current is a result of enhanced hole injection from multi-gate p-channel transistors with interdigitated source and drain. The electron current generated from impact ionization near the drain forward biases the source junctions, causing hole injection to the substrate. The current is sensitive to the supply voltage and temperature. Consequently, unanticipated failures may occur at the high voltages and temperatures encountered during burn-in. Design and process solutions are discussed.<> View full abstract»

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  • A 2- mu m BiCMOS process utilizing selective epitaxy

    Publication Year: 1988 , Page(s): 567 - 569
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (277 KB)  

    A 2- mu m BiCMOS process designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar structure with an estimated cutoff frequency of 5 GHz and nonoptimized vertical p-n-p structure into a 2- mu m CMOS process with a poly-to-n/sup +/ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps and with no change to the critical process parameters which determine the performance of the MOS transistors. View full abstract»

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  • Electron space-charge effects on high-frequency performance of AlGaAs/GaAs HBTs under high-current-density operation

    Publication Year: 1988 , Page(s): 570 - 572
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    The high-frequency characteristics of AlGaAs/GaAs heterojunction bipolar transistors (HBTs) under high-current-density biasing condition are investigated in conjunction with the electron space charge in the collector depletion layer. A significant increase in cutoff frequency f/sub t/ and maximum oscillation frequency f/sub max/ at the early stage of the base push-out was observed in HBTs with a lightly doped n-type collector structure, and is attributed to the collector depletion layer widening and the enhancement of the velocity overshoot effect caused by the increasing electron density.<> View full abstract»

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  • Leakage-current-induced hot-carrier degradation of p-channel MOSFETs

    Publication Year: 1988 , Page(s): 573 - 575
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB)  

    Leakage-current-induced hot-carrier effects have been observed during stressing of p-channel MOSFETs in the OFF state with V/sub GS/>0 V and V/sub DS/<0 V. This mode of stressing results in increased leakage current and a positive shift in the value of V/sub GS/, corresponding to the onset of avalanche breakdown of the drain junction. These effects are related to generation of interface states near the drain in forward-mode operation. By comparison, conventional stressing in the ON state with V/sub GS/<0 V and V/sub DS/<0 V resulted in little change in these p-channel MOSFET characteristics.<> View full abstract»

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  • Thin-film transistors incorporating a thin, high-quality PECVD SiO/sub 2/ gate dielectric

    Publication Year: 1988 , Page(s): 576 - 578
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    Thin-film transistors (TFTs) have been made that incorporate a thin ( approximately 380 AA), high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO/sub 2/ film as the gate dielectric in a staggered-inverted structure. Threshold voltages and mobilities have been found to be in the range of 1.6-2.4 V and 0.20-0.25 cm/sup 2/ V/sup -1/ s/sup -1/, respectively, where the exact values are dependent on the measurement technique used. Very low gate leakage currents (<10/sup -11/ A) were recorded when measured using a ramped I-V technique, even for electric fields as high as 5*10/sup 6/ V/cm.<> View full abstract»

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  • Leakage current degradation in n-MOSFETs due to hot-electron stress

    Publication Year: 1988 , Page(s): 579 - 581
    Cited by:  Papers (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    The field-induced drain-leakage current can become significant in NMOS devices with thin gate oxides. This leakage current component is found to be more prominent in devices with gate-drain overlap and can increase considerably with hot-electron stress. A method which shows how measuring the gate voltage needed to obtain a constant leakage value of 0.1 nA can yield useful information on the interface charge trap density is discussed.<> View full abstract»

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  • Direct tungsten on silicon dioxide formed by RF plasma-enhanced chemical vapor deposition

    Publication Year: 1988 , Page(s): 582 - 584
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    RF plasma-enhanced chemical vapor deposition (PECVD) has been used to deposit blanket tungsten on silicon dioxide for MOS gate formation. A range of deposition conditions are investigated. A postdeposition high-temperature anneal is necessary to reduce the resistivity and improve the adhesion of the film. Capacitors fabricated with the tungsten gate show good electrical properties with no apparent detrimental effects caused by the presence of either the plasma or fluorine during the deposition.<> View full abstract»

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  • Transit-time reduction in AlGaAs/GaAs HBTs utilizing velocity overshoot in the p-type collector region

    Publication Year: 1988 , Page(s): 585 - 587
    Cited by:  Papers (25)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (270 KB)  

    The effect of electron-velocity overshoot in a p-type GaAs collector on the transit-time reduction of AlGaAs/GaAs HBTs (heterojunction bipolar transistors) is investigated. A cutoff frequency improvement of about 30% over the conventional n-type GaAs collector was obtained in p-type collector HBTs for the same collector depletion-layer width. A significant increase in electron velocity in the p-type GaAs collector layer was confirmed by a simple analysis.<> View full abstract»

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  • Drain-avalanche and hole-trapping induced gate leakage in thin-oxide MOS devices

    Publication Year: 1988 , Page(s): 588 - 590
    Cited by:  Papers (26)  |  Patents (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (289 KB)  

    Leakage current components due to band-to-band tunneling and avalanche breakdown in thin-oxide (90-160 AA) gated-diode structures are discussed. Experimental results show that while the band-to-band tunneling current is not sensitive to channel doping concentration, the avalanche current is sensitive to channel doping concentration in the range of 10/sup 16/ to 10/sup 17/ cm/sup -3/. For oxides thicker than 110 AA, the gate current is found to be dominated by hot-hole injection and for oxides thinner than 110 AA the gate current is dominated by Fowler-Nordheim electron tunneling. After hot-hole injection, the gate oxide exhibits significant low-level leakage, which is explained by the barrier-lowering effect caused by the trapped holes in the oxide.<> View full abstract»

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  • Application of ink jet technology on photovoltaic metallization

    Publication Year: 1988 , Page(s): 591 - 593
    Cited by:  Papers (8)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (149 KB)  

    Computer-controlled ink-jet assisted metallization of the grid pattern of solar cells with metallo-organic decomposition (MOD) silver inks offers a maskless alternative method to conventional photolithographic thin-film technology and screen-printing technology. This method can provide low-cost, fine-resolution reduction in process complexity by direct ink-jet patterning, avoidance of degradation of p-n junctions by firing at low temperature (350 degrees C), and uniform line film on rough-surface solar cells (unpolished solar cells for low-cost purposes). The metallization process involves jet-printed metallo-organic inks, belt furnace firing, and thermal spiking. With titanium thin-film underlayer as an adhesion promoter and multilayer ink jet printing, solar cells of 8.08% average efficiency without AR coating can be obtained. This efficiency value is approximately equal to that of thin-film metallized solar cells of the same lot.<> View full abstract»

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  • Electrical properties of Ga-implanted Si p/sup +/-n shallow junctions fabricated by low-temperature rapid thermal annealing

    Publication Year: 1988 , Page(s): 594 - 597
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (346 KB)  

    p/sup +/-n shallow-junction diodes were fabricated using on-axis Ga/sup 69/ implantation into crystalline and preamorphized Si, at energies of 25-75 keV for a dose of 1*10/sup 15//cm/sup 2/, which is in excess of the dosage (2*10/sup 14//cm/sup 2/) required to render the implanted layer amorphous. Rapid thermal annealing at 550-600 degrees C for 30 s resulted in the solid-phase epitaxial (SPE) regrowth of the implanted region accompanied by high Ga activation and shallow junction (60-130 nm) formation. Good diode electrical characteristics for the Ga implantation into crystalline Si were obtained; leakage current density of 1-1.5 nA/cm/sup 2/ and ideality factor of 1.01-1.03. Ga implantation into preamorphized Si resulted in a two to three times decrease in sheet resistance, but a leakage current density orders of magnitude higher.<> View full abstract»

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  • AlGaAs/GaAs HBTs fabricated by a self-alignment technology using polyimide for electrode separation

    Publication Year: 1988 , Page(s): 598 - 600
    Cited by:  Papers (19)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (227 KB)  

    A self-aligned HBT (heterojunction bipolar transistor) technology using polymide for insulating the emitter contact from the base contact is described. A 1- mu m emitter-width HBT with maximum oscillation frequency of 86 GHz was successfully fabricated. This processing was also applied to fabricate frequency-divider ICs. An operating frequency of 18 GHz was obtained with good reproducibility.<> View full abstract»

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  • p/sup +/-AlInAs/InP junction FETs by selective molecular beam epitaxy

    Publication Year: 1988 , Page(s): 601 - 603
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (299 KB)  

    p/sup +/-AlInAs/InP junction field-effect transistors (FETs) have been fabricated in semi-insulating InP:Fe using ion implantation and a selective molecular-beam epitaxy (MBE) technique. Current-voltage measurements on 4.0- mu m gate-length devices show a zero-gate-bias transconductance of 41 mS/mm, and RF measurements indicate a unity-power-gain frequency of 3.2 GHz. These results indicate that the selective growth method is a viable technique for fabricating high-frequency, high-power junction FETs in the InP-based materials system.<> View full abstract»

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  • High-performance In/sub 0.08/Ga/sub 0.92/As MESFETs on GaAs

    Publication Year: 1988 , Page(s): 604 - 606
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    In/sub 0.08/Ga/sub 0.92/As MESFETs were grown in GaAs View full abstract»

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  • An investigation of the optoelectronic response of GaAs/InGaAs MSM photodetectors

    Publication Year: 1988 , Page(s): 607 - 609
    Cited by:  Papers (30)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (291 KB)  

    It is shown that the planar metal-semiconductor-metal photodetectors on InGaAs/InP with a strained GaAs top layer are promising candidates for optoelectronic integration of long-wavelength (1.3-1.55 mu m) fiber-optic components, combining speed of response (8.5-GHz bandwidth) with a simple technology (only four processing steps were required for the presented detector). Some low-frequency gain was observed at high bias voltages along with a low-frequency increase in noise above that expected from shot noise.<> View full abstract»

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  • AlGaAs/InGaAs/GaAs quantum-well power MISFET at millimeter-wave frequencies

    Publication Year: 1988 , Page(s): 610 - 612
    Cited by:  Papers (9)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (243 KB)  

    An AlGaAs/InGaAs/GaAs quantum-well MISFET developed for power operation at millimeter-wave frequencies is described. The InGaAs channel is heavily doped to increase the sheet carrier density, resulting in a maximum current density of 700 mA/mm with a transconductance of 480 mS/mm. The 0.25- mu m*50- mu m device delivers a power density of 0.76 W/mm with 3.6-dB gain and 19% power-added efficiency at 60 GHz. At 5.2 dB gain, the power density is 0.55 W/mm. A similar device built on an undoped InGaAs channel had much poorer power performance and no speed advantage.<> View full abstract»

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  • Dependence of Al-Si/Si contact resistance on substrate surface orientation

    Publication Year: 1988 , Page(s): 613 - 615
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    The dependence of Si growth on substrate orientation in the aluminium-silicon system is investigated. The Si epitaxial growth is found to show a strong dependence on the substrate surface orientation similar to the growth from Si-implanted amorphous Si. The Si growth at contact cuts changes in its quantity with substrate orientation, and Si SPE (solid-phase epitaxy) does not occur seriously on <111>-oriented substrates under the temperature in the experiment. As a result, the contact resistance of <100>-oriented samples increases rapidly with sintering time and its dispersion also increases, while those of <111>-oriented samples stay constant. The <111>-oriented surface is the most prominent for the contact-resistance stability.<> View full abstract»

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  • Charge transport and trapping characteristics in thin nitride-oxide stacked films

    Publication Year: 1988 , Page(s): 616 - 618
    Cited by:  Papers (8)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (271 KB)  

    A charge transport and trapping model for thin nitride-oxide stacked films between silicon substrates and polysilicon gates is proposed. Nitride-oxide stacked films can be thought of as an oxide film with electron trapping at the nitride/oxide interface. The density of electron trapping is determined by the current-continuity requirement. The electron trapping reduces the leakage current and helps to lower the incidence of early failures for nitride-oxide stacked films.<> View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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