Scheduled System Maintenance:
On May 6th, single article purchases and IEEE account management will be unavailable from 8:00 AM - 12:00 PM ET (12:00 - 16:00 UTC). We apologize for the inconvenience.
By Topic

Solid-State Circuits, IEEE Journal of

Issue 2 • Date Feb. 2009

Filter Results

Displaying Results 1 - 25 of 38
  • Table of contents

    Publication Year: 2009 , Page(s): C1 - C4
    Save to Project icon | Request Permissions | PDF file iconPDF (44 KB)  
    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits publication information

    Publication Year: 2009 , Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (39 KB)  
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2009 , Page(s): 317 - 318
    Save to Project icon | Request Permissions | PDF file iconPDF (43 KB)  
    Freely Available from IEEE
  • New Associate Editor

    Publication Year: 2009 , Page(s): 319
    Save to Project icon | Request Permissions | PDF file iconPDF (160 KB)  
    Freely Available from IEEE
  • A Low-Power, Linearized, Ultra-Wideband LNA Design Technique

    Publication Year: 2009 , Page(s): 320 - 330
    Cited by:  Papers (68)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (711 KB) |  | HTML iconHTML  

    This work proposes a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, and analyzes its performance with Volterra series. The linearization technique is applied to an ultra-wideband (UWB) cascode common gate Low Noise Amplifier (CG-LNA), and two additional reference designs are implemented to evaluate the linearization technique - a standard (without linearization) cascode CG-LNA and a single-transistor CG-LNA. The single-transistor CG-LNA achieves +6.5 to +9.5 dBm IIP3, 10 dB (max.) gain, and 2.9 dB (min.) NF over a 3-11 GHz bandwidth (BW); the LNA consumes 2.4 mW from a 1.3 V supply. The cascode linearized LNA achieves +11.7 to +14.1 dBm IIP3, 11.6 dB (max.) gain, and 3.6 dB (min.) NF over 1.5 to 8.1 GHz; the cascode LNA consumes 2.62 mW from a 1.3 V supply. Experimental results show that the linearization technique improves the cascode LNA's IIP3 by a factor of 3.5 to 9 dB over a 2.5-10 GHz frequency range. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems

    Publication Year: 2009 , Page(s): 331 - 343
    Cited by:  Papers (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1322 KB) |  | HTML iconHTML  

    A 0.13-mu m CMOS fourth-order notch filter for the rejection of the 5-6 GHz interference in UWB front-ends is reported. The filter is integrated into an analog front-end for Mode #1 UWB. A thorough analysis based on a simplified model of the filter is carried out. An algorithm for the automatic tuning and calibration of the filter is also discussed and demonstrated. Two versions of the circuit are designed and fabricated: the first comprises a low-noise amplifier and the filter, and the second expands it to a complete front-end. In the latter version the filter was also redesigned. The filter provides more than 35 dB of attenuation and has a tuning range of 900 MHz, adding less than 30% power consumption to the LNA. The out-of-band IIP3 (higher than -13.2 dBm with the filter off) takes a 9-dB advantage from the filter and the compression of the gain due to the out-of-band blocker is reduced by at least 6 dB in the complete front-end. The conversion gain of the front-end is 25 dB per channel, its average noise figure is lower than 6.2 dB, and its in-band 1-dB compression point is higher than - 30 dBm at a power consumption of 32 mW. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5–6 GHz CMOS LNA

    Publication Year: 2009 , Page(s): 344 - 353
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB) |  | HTML iconHTML  

    The increasing mask costs of modern scaled CMOS makes silicon area precious. Meanwhile, the lowering oxide thickness seriously toughens ESD protection of RF circuits, pushing towards area-demanding inductor-based ESD protection techniques. This paper presents a transformer-based ESD protection technique for inductor-based LNAs. With no area penalty, an ESD protection level of 4.5 kV HBM is achieved. Introducing two-stage protection increases the robustness up to 7.3 kV, maintaining excellent RF performance. Further it extends the TLP protection level from 3.2 to 5 A. A noise figure of 2.6 dB is achieved with a power gain of 14.8 dB, while consuming 6.5 mW. The technique serves as a solution for low-area highly protected LNAs in deep-submicron CMOS. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders

    Publication Year: 2009 , Page(s): 354 - 370
    Cited by:  Papers (50)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1230 KB) |  | HTML iconHTML  

    This paper presents a RF to DC conversion model for multi-stage rectifiers in UHF RFID transponders. An equation relating the RF power available from the antenna to the DC output voltage produced by a multi-stage rectifier is presented. The proposed model includes effects of the nonlinear forward voltage drop in diodes and impedance matching conditions of the antenna to rectifier interface. Fundamental frequency impedance approximation is used to analyze the resistance of rectifying diodes; parasitic resistive loss components are also included in the analysis of rectifier input resistance. The closed form equation shows insights into design parameter tradeoffs, such as power available from the antenna, antenna radiation resistance, the number of diodes, DC load current, parasitic resistive loss components, diode and capacitor sizes, and frequency of operation. Therefore, it enables the optimization of rectifier parameters for impedance matching with a low-cost printed antenna and shunt tuning inductor, in order to improve the RF to DC conversion efficiency and the operational distance of UHF RFID transponders. Three diode doublers and three multistage rectifiers were fabricated in a 130 nm CMOS process with custom no-mask added Schottky diodes. Measurements of the test IC are in good agreement with the proposed model. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Wideband Power Detection System Optimized for the UWB Spectrum

    Publication Year: 2009 , Page(s): 371 - 381
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (858 KB) |  | HTML iconHTML  

    A wideband radio-frequency (RF) power detection system is presented. The detection technique uses NMOS devices operating in the triode regime to generate an average current proportional to RF input power; this current is converted to voltage and amplified using a piecewise linear logarithmic approximation. Optimization of the NMOS devices is discussed, and a method of gain control is proposed for compensation of temperature and process variation. The power detector occupies an active area of 0.36 mm2 in a 0.18 mum CMOS process and consumes 10.8 mW from the power supply. Error between the output and a linear-in-dB best-fit curve is plusmn2.4 dB for a 20 dB input range, when measured at discrete frequencies. The output response is frequency independent, varying by less than 1.8 dB for a fixed input power as frequency is swept across the UWB spectrum. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Single-Chip Ultra-Wideband Receiver With Silicon Integrated Antennas for Inter-Chip Wireless Interconnection

    Publication Year: 2009 , Page(s): 382 - 393
    Cited by:  Papers (36)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1497 KB) |  | HTML iconHTML  

    A single-chip ultra-wideband (UWB) receiver was developed using 0.18 mum CMOS technology, and inter-chip wireless data communication by integrated antennas was confirmed. Timing pulse and data pulse with on-off keying were alternately sent from a transmitting antenna. Double Gaussian monocycle pulse (GMP) template generators performed detections of timing and data pulses. A single GMP template, whose probability distribution of the pulse repetition cycle is given by Gaussian, showed a random jitter of 4.87 ps. Dual-Dirac model could explain the probability distribution of the cycle of double GMP template. Obtained random jitter and deterministic jitter were 4.6 ps and 14.4 ps, respectively. The receiver successfully recovered 200 Mbps data at the distance of 0.5 mm. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna

    Publication Year: 2009 , Page(s): 394 - 403
    Cited by:  Papers (38)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1390 KB) |  | HTML iconHTML  

    This paper presents a novel impulse radio based ultra-wideband transmitter. The transmitter is designed in 0.18 mum CMOS process realizing extremely low complexity and low power. It exploits the 6-to-10 GHz band to generate short duration bi-phase modulated UWB pulses with a center frequency of 8 GHz. No additional RF filtering circuits are required since the pulse generator circuit itself has the functionality of pulse shaping. Generated pulses comply with the FCC spectral emission mask. Measured results show that the transmitter consumes 12 pJ/b to achieve a maximum pulse repetition rate of 750 Mb/s. An optional embedded on-chip antenna and a power amplifier operating in 6-10 GHz band are also designed and investigated as a future low cost solution for very short distance IR-UWB communications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Combined Linear and \Delta -Modulated Switch-Mode PA Supply Modulator for Polar Transmitters

    Publication Year: 2009 , Page(s): 404 - 413
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (931 KB) |  | HTML iconHTML  

    A combined linear and delta-modulated (DeltaM) switch-mode PA supply modulator for polar transmitters in wireless handsets is designed in a 0.25 mum CMOS process. The modulator employs a DeltaM switch-mode DC-DC buck converter to enhance the efficiency of a linear regulator at backed-off supply voltages and powers. The delta-modulator's noise-shaping characteristic, linear regulator's power supply rejection, digital pre-emphasis of the input envelope, and a closed-loop amplitude path from the PA output are simultaneously used to achieve state-of-the-art modulator performance. The presented supply modulator follows the input signal's envelope with 20 dB output dynamic range, maximum efficiency of 75.5% at an output power of 30.8 dBm, and 75 dB SFDR for envelope signals up to 4 MHz occupied RF bandwidth. For a 1625 kb/s 8 PSK RF input signal at 900 MHz, polar modulation of a commercial low-power GSM-900 PA provides 10 dB ACPR improvement. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 3.1 GHz–8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18- \mu m CMOS Process

    Publication Year: 2009 , Page(s): 414 - 426
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2134 KB) |  | HTML iconHTML  

    This paper presents the design and integration of a fully-integrated dual-conversion zero-IF2 CMOS transceiver for 9-band MB-OFDM UWB systems from 3.1 GHz to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single combined mixer for both RF down-conversion in RX and up-conversion in TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18- mum CMOS process, the receiver measures maximum S11 of - 13 dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatches of the receiver chain are measured to be 0.8 dB and 4 deg, respectively. The transmitter achieves a minimum output P-1 dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than - 46.5 dBc. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

    Publication Year: 2009 , Page(s): 427 - 435
    Cited by:  Papers (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1436 KB) |  | HTML iconHTML  

    An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop bandwidth tracking is described. In order to minimize loop bandwidth variations resulting from changes in the LC-VCO gain, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a servo loop which sets the charge-pump current to be inversely proportional to the square of the oscillation frequency. The combination of these techniques maintains a constant loop bandwidth over a wide range of operating frequencies. Fabricated in a 0.13 mum CMOS technology, the prototype chip measures less than plusmn4% variation in KVCOmiddotICP / N (equivalent to the variation in PLL loop bandwidth) for an operating frequency range of 3.1 to 3.9 GHz. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS

    Publication Year: 2009 , Page(s): 436 - 449
    Cited by:  Papers (12)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1790 KB) |  | HTML iconHTML  

    A wideband LC PLL in 45-nm SOI CMOS technology is presented that has a center frequency of 12.4 GHz and 1.2 octave locking range. The wideband operation is achieved by switching mutual inductances within the inductor coil of the LC oscillator. To minimize resistive switching losses, the inductor coil consists of a non-switchable primary coil and two isolated secondary coils with series switches. When the switches are closed, the overall inductance reduces because of the switched mutual inductances. Three inductor bands, each consisting of 16 switched capacitor sub-bands, span a frequency range from 7.3 to 17.5 GHz. The in-band phase noise measured after a 1/4 divider is better than -107 dBc/Hz at 1 MHz offset frequency in the entire locking range. The PLL is fully differential and its core has a power consumption of 25 mW at the highest oscillation frequency. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Systematic Transistor and Inductor Modeling for Millimeter-Wave Design

    Publication Year: 2009 , Page(s): 450 - 457
    Cited by:  Papers (30)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (992 KB) |  | HTML iconHTML  

    This paper proposes a simulation-based modeling methodology that provides greater flexibility in the design and layout of millimeter-wave CMOS circuits than measurement- based models do. A physical model for the metallization capacitances of the transistors is described and new layout techniques are introduced that exploit these capacitances to improve the circuit performance. The accuracy of the models is verified by the design and measurement of five oscillators operating in the range of 40 GHz to 130 GHz in 90-nm CMOS technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator

    Publication Year: 2009 , Page(s): 458 - 472
    Cited by:  Papers (62)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3289 KB) |  | HTML iconHTML  

    An operational transconductance amplifier (OTA) is a major building block and consumes most of the power in switched-capacitor (SC) circuits, but it is difficult to design low-voltage OTAs in scaled CMOS technologies. Instead of using an OTA, this paper proposes an inverter-based SC circuit and its application to low-voltage, low-power delta-sigma (DeltaSigma) modulators. Detailed analysis and design optimizations are also provided. Three inverter-based DeltaSigma modulators are implemented for an implantable pacemaker, a CMOS image sensor, and an audio codec. The modulator-I for an implantable pacemaker achieves 65-dB peak-SNDR for 120-Hz bandwidth consuming 0.73 muW with 1.5 V supply. The modulator-II for a CMOS image sensor implemented with 320-channel parallel ADC architecture achieves 63-dB peak-SNDR for 8-kHz bandwidth consuming 5.6 muW for each channel with 1.2-V supply. The modulator-III for an audio codec achieves 81-dB peak-SNDR with 20-kHz bandwidth consuming 36 muW with 0.7-V supply. The prototype DeltaSigma modulators achieved high power efficiency maintaining sufficient performances for practical applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and Measurement of a CT \Delta \Sigma ADC With Switched-Capacitor Switched-Resistor Feedback

    Publication Year: 2009 , Page(s): 473 - 483
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1205 KB) |  | HTML iconHTML  

    The performance of traditional continuous-time (CT) delta-sigma (DeltaSigma) analog-to-digital converters (ADCs) is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback digital-to-analog converters (DACs). To mitigate that effect, we propose a modified switched-capacitor (SC) feedback DAC technique, with a variable switched series resistor (SR). The architecture has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators. A theoretical investigation is carried out which provides new insight into the synthesis of switched-capacitor with switched series resistor (SCSR) DACs with a specified reduction of the pulse-width jitter sensitivity and minimal power consumption and complexity. To demonstrate the concept and to verify the reduced pulse-width jitter sensitivity a 5 mW, 312 MHz, second order, low-pass, 1-bit, CT DeltaSigma modulator with SCSR feedback was implemented in a 1.2 V, 90 nm, RF-CMOS process. An SNR of 66.4 dB and an SNDR of 62.4 dB were measured in a 1.92 MHz bandwidth. The sensitivity to wideband clock phase noise was reduced by 30 dB compared to a traditional switched-current (SI) return-to-zero (RZ) DAC. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors

    Publication Year: 2009 , Page(s): 484 - 494
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (783 KB) |  | HTML iconHTML  

    The interaction between substrate and devices is normally neglected during the design of on-chip MOS decoupling capacitors (decaps). However, it may significantly influence the decap performance to reduce high-frequency power supply noise. In this paper we propose a novel six-parameter analytical decap model which accounts for substrate and device interactions. Our model has been compared against state-of-the-art decap models. Moreover, it has been extensively validated through simulations and measurements. For 65 nm LP-CMOS, a close correlation has been obtained over a large frequency range from 10 MHz up to 10 GHz. Furthermore, we introduce the maximum decap admittance as a new metric for decap performance qualification. Closed-form expressions have been derived to calculate maximum admittance. Finally, we determine the relationship between relevant figure-of-merit parameters for decap design optimization. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1-V +31 dBm IIP3, Reconfigurable, Continuously Tunable, Power-Adjustable Active-RC LPF

    Publication Year: 2009 , Page(s): 495 - 508
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2115 KB) |  | HTML iconHTML  

    This paper proposes a biquad design methodology and presents a baseband low-pass filter for wireless and wireline applications with reconfigurable frequency response (Chebyshev/Inverse Chebyshev), selectable order (1st/3rd/5th), continuously tunable cutoff frequency (1-20 MHz), and adjustable power consumption (3-7.5 mW). A discrete capacitor array coarsely tunes the low-pass filter, and a novel continuous impedance multiplier (CIM) then finely tunes the filter. Resistive/capacitive networks select between the Chebyshev and inverse Chebyshev approximation types. Also, a new stability metric for biquads, minimum acceptable phase margin (MAPM), is presented and discussed in the context of filter compensation and passband ripple considerations. Experimental results yield an IIP3 of 31.3 dBm, a THD of -40 dB at 447 mVpk, diff input signal amplitude, and a DR of 71.4 dB. The filter's tunable range covers frequencies from 1 MHz to 20 MHz. In Inverse Chebyshev mode, the filter achieves a passband group delay variation less than plusmn2.5%. The design is fabricated in 0.13 mum CMOS, occupies 1.53 mm2 , and operates from a 1-V supply. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Single-Inductor Step-Up DC-DC Switching Converter With Bipolar Outputs for Active Matrix OLED Mobile Display Panels

    Publication Year: 2009 , Page(s): 509 - 524
    Cited by:  Papers (34)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1679 KB) |  | HTML iconHTML  

    A single-inductor step-up DC-DC switching converter with bipolar outputs is implemented for active-matrix OLED mobile display panels. The positive output voltage is regulated by a boost operation with a modified comparator control (MCC), and the negative output voltage is regulated by a charge-pump operation with a proportional-integral (PI) control. The proposed adaptive current-sensing technique successfully supports the implementation of the proposed converter topology and enables the converter to work in both discontinuous-conduction mode (DCM) and continuous-conduction mode (CCM). In addition, with the MCC method, the converter can guarantee a positive output voltage that has both a fast transient response of the comparator control and a small output voltage ripple of the PWM control. A 4.1 mm2 converter IC fabricated in a 0.5 mum power BiCMOS process operates at a switching frequency of 1 MHz with a maximum efficiency of 82.3% at an output power of 330 mW. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Rail-To-Rail Class-AB Amplifier With an Offset Cancellation for LCD Drivers

    Publication Year: 2009 , Page(s): 525 - 537
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1081 KB) |  | HTML iconHTML  

    A rail-to-rail amplifier with an offset cancellation, which is suitable for high color depth and high-resolution liquid crystal display (LCD) drivers, is proposed. The amplifier incorporates dual complementary differential pairs, which are classified as main and auxiliary transconductance amplifiers, to obtain a full input voltage swing and an offset canceling capability. Both offset voltage and injection-induced error, due to the device mismatch and charge injection, respectively, are greatly reduced. The offset cancellation and charge conservation, which is used to reduce the dynamic power consumption, are operated during the same time slot so that the driving period does not need to increase. An experimental prototype amplifier is implemented with 0.35-mum CMOS technology. The circuit draws 7.5 muA static current and exhibits the settling time of 3 mus, for a voltage swing of 5 V under a 3.4 kOmega resistance, and a 140 pF capacitance load with a power supply of 5 V. The offset voltage of the amplifier with offset cancellation is 0.48 mV. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Slew Controlled LVDS Output Driver Circuit in 0.18 \mu m CMOS Technology

    Publication Year: 2009 , Page(s): 538 - 548
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1177 KB) |  | HTML iconHTML  

    This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 mum CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 Omega resistor with an output voltage swing of VOD = 400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 mm2 and the measured output jitter is sigmarms = 4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load RC time constant. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-Speed Single-Ended Parallel Link Based on Three-Level Differential Encoding

    Publication Year: 2009 , Page(s): 549 - 557
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1322 KB) |  | HTML iconHTML  

    An encoding scheme for high-speed single-ended parallel transceiver system is presented. Compared to the 50% I/O pin utilization of the conventional differential encoding, the proposed system employs 3-level differential coding to increase the utilization to 75% and 93% using a group of four and six conductors, respectively. The proposed coding scheme also reduces the effects of inter-symbol interference (ISI), removes reference ambiguity, and reduces power line fluctuations at the transmitter side. Using simple encoder/decoder, the proposed scheme enables multiple drivers at the transmitter to recycle the same current, reducing power consumption. To validate the proposed system, a parallel link was designed in 0.18 mum CMOS process. The chip implements the coding algorithm over four conductors and achieves a data rate of 4.2 Gb/s/pin while dissipating 17.1 mW/Gb/s. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and Analysis of Actively-Deskewed Resonant Clock Networks

    Publication Year: 2009 , Page(s): 558 - 568
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1317 KB) |  | HTML iconHTML  

    Active deskewing is an important technique for managing variability in clock distributions but introduces latency and power-supply-noise sensitivity into the resulting networks. In this paper, an adaptively deskewed resonant clock network, based on an injection-locked distributed differential oscillator, is described, in which the delay lines required for deskewing are incorporated into the injection-lock source, dramatically improving jitter immunity. A power management system based on automatic amplitude control of the resonant grid further enhances energy efficiency. A prototype system operates at a nominal 2-GHz frequency in a 0.18 mum technology with on-chip jitter and skew measurement circuits and with more than 25 pF/mm2 of clock loading. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan