# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 33

Publication Year: 2009, Page(s):C1 - C4
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2009, Page(s): C2
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• ### Proper Referencing of Prior Art

Publication Year: 2009, Page(s): 161
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• ### Trap and Inversion Layer Mobility Characterization Using Hall Effect in Silicon Carbide-Based MOSFETs With Gate Oxides Grown by Sodium Enhanced Oxidation

Publication Year: 2009, Page(s):162 - 169
Cited by:  Papers (24)
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Low-temperature MOS-gated Hall measurements and gated diode capacitance-voltage (C-V) measurements were performed to characterize both trap density and Hall mobility on 4H-silicon carbide MOSFETs with gate oxides grown by sodium enhanced oxidation (SEO) and thermally grown in N2O. The interface trap density Dit was determined close to the conduction band edge by Hall effect m... View full abstract»

• ### High-Voltage GaAs Photovoltaic Laser Power Converters

Publication Year: 2009, Page(s):170 - 175
Cited by:  Papers (32)  |  Patents (6)
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The main drawback of photovoltaic (PV) laser power converters based on GaAs material is the low output voltage, which is often insufficient to power electronic circuits directly. Aside from the use of a dc-dc converter in combination with a single PV converter, it is possible to boost the voltage by the monolithic serial interconnection of several converter segments on a single chip, often called ... View full abstract»

• ### Experimental Study and Statistical Analysis of Solution-Shearing Processed Organic Transistors Based on an Asymmetric Small-Molecule Semiconductor

Publication Year: 2009, Page(s):176 - 185
Cited by:  Papers (23)
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Solution processed organic field-effect transistors (SPOFETs) are crucial for realizing low-cost large-area/ubiquitous flexible electronics. Currently, both soluble high-mobility organic semiconductors and efficient solution processes are in demand. In this paper, we report the systematic experimental study and statistical modeling/analysis for the SPOFETs based on an asymmetric small-molecule org... View full abstract»

• ### Filament Conduction and Reset Mechanism in NiO-Based Resistive-Switching Memory (RRAM) Devices

Publication Year: 2009, Page(s):186 - 192
Cited by:  Papers (176)  |  Patents (5)
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The physical understanding of the programming and reliability mechanisms in resistive-switching memory devices requires a detailed characterization of the electrical and thermal conduction properties in the low-resistance state of the memory cell. The aim of this paper is the characterization of the conductive filament (CF), which controls the localized current flow in the low resistive state of t... View full abstract»

• ### Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices

Publication Year: 2009, Page(s):193 - 200
Cited by:  Papers (204)  |  Patents (44)
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This paper addresses the numerical modeling of reset programming in NiO-based resistive-switching memory. In our model, we simulate electrical conduction and heating in the conductive filament (CF), which controls the resistance of the low resistive (or set) state, accounting for CF thermal-activated dissolution. Employing CF electrical and thermal parameters, which were previously characterized o... View full abstract»

• ### Band Structure Effects on the Scaling Properties of [111] InAs Nanowire MOSFETs

Publication Year: 2009, Page(s):201 - 205
Cited by:  Papers (44)
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We have investigated the scaling properties of [111] InAs nanowire MOSFETs in the ballistic limit. The nanowire band structure has been calculated with an sp3d5 s* tight-binding model for nanowire diameters between 2 and 25 nm. Both the effective band gap and the effective masses increase with confinement. Using the atomistic dispersion relations, the ballistic currents and c... View full abstract»

• ### Anomalous Gate-Edge Leakage Current in nMOSFETs Caused by Encroached Growth of Nickel Silicide and Its Suppression by Confinement of Silicidation Region Using Advanced $hbox{Si}^{+}$ Ion-Implantation Technique

Publication Year: 2009, Page(s):206 - 213
Cited by:  Papers (5)
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The anomalous gate-edge leakage current in n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs), which is caused by the encroached growth of nickel silicide across the p-n junction, is first reported. Furthermore, this encroached growth, which is caused by the isotropic and rapid diffusion of Ni atoms during the silicidation annealing, is successfully suppressed by the advanced ... View full abstract»

• ### A CMOS Image Sensor With In-Pixel Two-Stage Charge Transfer for Fluorescence Lifetime Imaging

Publication Year: 2009, Page(s):214 - 221
Cited by:  Papers (24)
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A CMOS image sensor for time-resolved fluorescence lifetime imaging with subnanosecond time resolution is presented. In order to analyze the fluorescence lifetime, the proposed CMOS image sensor has two charge transfer stages using a pinned photodiode structure in which the first charge transfer stage is for the time-resolved sifting of fluorescence in all the pixels simultaneously and the second ... View full abstract»

• ### Analysis of the Role of Current, Temperature, and Optical Power in the Degradation of InGaN-Based Laser Diodes

Publication Year: 2009, Page(s):222 - 228
Cited by:  Papers (3)
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This paper reports on the degradation of InGaN-based laser diodes for Blu-ray technology. The devices have been submitted to stress under: 1) constant current, different temperatures; 2) high temperature, no bias; and 3) constant temperature, several current levels. The tests carried out within this paper demonstrate that stress determines the increase in the threshold current, according to the sq... View full abstract»

• ### An Improved Optical Feedback Pixel Driver Circuit

Publication Year: 2009, Page(s):229 - 235
Cited by:  Papers (14)  |  Patents (1)
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An improved optical feedback circuit is proposed with only a few components and a wide range of V data voltages. Its operation is verified by simulation using the HSPICE simulator, PSIA2 thin-film transistor (TFT) model, and our previously published light-impact model of polycrystalline TFTs. In addition, the new optical feedback pixel driver (OFPD) is compared with previously pu... View full abstract»

• ### Isolation of NBTI Stress Generated Interface Trap and Hole-Trapping Components in PNO p-MOSFETs

Publication Year: 2009, Page(s):236 - 242
Cited by:  Papers (45)
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In this paper, a simple phenomenological technique is used to isolate the hole-trapping and interface trap generation components during negative bias temperature instability (NBTI) stress in plasma nitrided oxide (PNO) p-MOSFETs. This isolation methodology reconciles the apparent differences between experimentally measured NBTI power-law time exponents obtained by ultrafast on-the-fly IDLIN View full abstract»

• ### Benchmark Tests for MOSFET Compact Models With Application to the PSP Model

Publication Year: 2009, Page(s):243 - 251
Cited by:  Papers (27)
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This paper presents the results of several qualitative ldquobenchmarkrdquo tests that were used to verify the physical behavior of the PSP model and its usefulness for future generations of CMOS IC design. These include newly developed tests and new experimental data stemming from low-power, RF, mixed-signal, and analog applications of MOSFETs. View full abstract»

• ### New Method for Evaluating Electric Field at Junctions of DRAM Cell Transistors by Measuring Junction Leakage Current

Publication Year: 2009, Page(s):252 - 259
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A new method for the analysis of dynamic random-access memory (DRAM) data-retention characteristics is developed. We extend a 1-D model of the bias dependence of the electric field in a p-n junction in DRAM to a 2-D model. The validity of the new model is confirmed by simulations and experiments. We then find that the electric-field strength in DRAM can be easily evaluated by measuring the substra... View full abstract»

• ### Modeling of Channel Potential and Subthreshold Slope of Symmetric Double-Gate Transistor

Publication Year: 2009, Page(s):260 - 266
Cited by:  Papers (32)
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A new physically based classical continuous potential distribution model, particularly considering the channel center, is proposed for a short-channel undoped body symmetrical double-gate transistor. It involves a novel technique for solving the 2-D nonlinear Poisson's equation in a rectangular coordinate system, which makes the model valid from weak to strong inversion regimes and from the channe... View full abstract»

• ### A Modified Charge-Pumping Method for the Characterization of Interface-Trap Generation in MOSFETs

Publication Year: 2009, Page(s):267 - 274
Cited by:  Papers (11)
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A novel recovery-free interface-trap measurement method is presented in detail. This method is the modification of the conventional charge pumping (CP) by extending the pulse low level to the stress-bias and minimizing the pulse high-level duty cycle to suppress the recovery effect. The method is applied to study the negative-bias temperature instability in p-MOSFETs. As compared with the conventi... View full abstract»

• ### Design Methodology and Protection Strategy for ESD-CDM Robust Digital System Design in 90-nm and 130-nm Technologies

Publication Year: 2009, Page(s):275 - 283
Cited by:  Papers (7)
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A design methodology and protection strategy for ESD charged-device-model (CDM) robust digital systems is presented using a scalable postbreakdown transistor macromodel for 90- and 130-nm technologies. The macromodel was implemented in a design tool to aid reliable chip design and used to predict function failure in three different system-on-chip design examples. Simulations agree well with failur... View full abstract»

• ### A Comprehensive Investigation of Analog Performance for Uniaxial Strained PMOSFETs

Publication Year: 2009, Page(s):284 - 290
Cited by:  Papers (9)
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This paper presents a comprehensive investigation of the analog performance for uniaxial strained PMOSFETs with sub -100 nm gate length. Through a comparison between co-processed strained and unstrained devices regarding important analog metrics such as transconductance to drain current ratio (g m/I d), dc gain, linearity, low-frequency noise, and device mismatc... View full abstract»

• ### Atomically Flat Silicon Surface and Silicon/Insulator Interface Formation Technologies for (100) Surface Orientation Large-Diameter Wafers Introducing High Performance and Low-Noise Metal–Insulator–Silicon FETs

Publication Year: 2009, Page(s):291 - 298
Cited by:  Papers (32)
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Technology to atomically flatten the silicon surface on (100) orientation large-diameter wafer and the formation technology of an atomically flat insulator film/silicon interface are developed in this paper. Atomically flat silicon surfaces composed of atomic terraces and steps are obtained on (100) orientation 200-mm-diameter wafers by annealing in pure argon ambience at 1200degC for 3... View full abstract»

• ### Geometry-Scalable Parasitic Deembedding Methodology for On-Wafer Microwave Characterization of MOSFETs

Publication Year: 2009, Page(s):299 - 305
Cited by:  Papers (5)
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This paper presents a geometry-scalable parasitic deembedding technique for on-wafer S-parameter measurements of silicon MOSFETs. The proposed methodology is based on the transmission-line theory and the cascade and parallel combinations of two-port networks. We use only one ¿reflect¿ and one ¿thru¿ dummy structure on a wafer to remove the feeding networks with arbitrary... View full abstract»

• ### Characterization of Three-Terminal Junctions Operated as In-Plane Gated Field-Effect Transistors

Publication Year: 2009, Page(s):306 - 311
Cited by:  Papers (5)
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The field-effect transistor operation of monolithic three-terminal junctions (TTJs) is demonstrated at room temperature. The TTJs are based on a modulation-doped GaAs/AlGaAs heterostructure with a 2-D electron gas situated 33 nm below the surface. By applying mask technology and wet chemical etching, several TTJs were fabricated, and the interplay between the TTJ geometry and the transistor charac... View full abstract»

• ### Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap

Publication Year: 2009, Page(s):312 - 320
Cited by:  Papers (18)
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We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-kappa/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios o... View full abstract»

• ### A New Fabrication and Assembly Process for Ultrathin Chips

Publication Year: 2009, Page(s):321 - 327
Cited by:  Papers (43)  |  Patents (3)
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A new ultrathin chip fabrication and assembly process, consisting of a preprocess module Chipfilm and a postprocess module Pick, Crack, and Place, is presented. In contrast to the established wafer thinning technique, the preprocessed wafer substrates are prepared with extremely narrow buried cavities beneath the chip areas at a well-defined distance from the wafer surface, thus precisely defining... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy