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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 2 • Date Feb. 2009

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Displaying Results 1 - 17 of 17
  • Table of contents

    Publication Year: 2009, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2009, Page(s): C2
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  • Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip

    Publication Year: 2009, Page(s):165 - 178
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (845 KB) | HTML iconHTML

    Latency-insensitive design is a methodology for system-on-chip (SoC) design that simplifies the reuse of intellectual property cores and the implementation of the communication among them. This simplification is based on a system-level protocol that decouples the intracore logic design from the design of the intercore communication channels. Each core is encapsulated within a shell, a synthesized ... View full abstract»

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  • Improving Simulated Annealing-Based FPGA Placement With Directed Moves

    Publication Year: 2009, Page(s):179 - 192
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1512 KB) | HTML iconHTML

    Simulated annealing remains a widely used heuristic for field-programmable gate array placement due, in part, to its ability to produce high-quality placements while accommodating complex objective functions. This paper discusses enhancements to annealing-based placement which improve upon both quality and run-time. Specifically, intelligent strategies for selecting and placing cells are intersper... View full abstract»

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  • A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control

    Publication Year: 2009, Page(s):193 - 206
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2449 KB) | HTML iconHTML

    As nanometer technology advances, the post chemical-mechanical polishing (CMP) topography variation control becomes crucial for manufacturing closure. To improve the CMP quality, dummy-feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and significantly increase the input data in the followin... View full abstract»

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  • Substrate Topological Routing for High-Density Packages

    Publication Year: 2009, Page(s):207 - 216
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1210 KB) | HTML iconHTML

    Off-chip substrate routing for high-density packages is on the critical path for time to market. Compared with on-chip routers, existing commercial tools for off-chip routing have lower routability and often result in a large number of unrouted nets for manual routing. In this paper, we explain why planar routing is still required with multiple routing layers for substrate routing and then propose... View full abstract»

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  • Incremental Improvement of Voltage Assignment

    Publication Year: 2009, Page(s):217 - 230
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (959 KB) | HTML iconHTML

    Design for low power has become a key requirement in today's System-on-a-Chip design, particularly for mobile applications. Multi-Vdd (MSV) is an effective method to reduce both leakage and dynamic powers. In a MSV design, cells of different supply voltages are often grouped into a small number of voltage islands, in order to avoid complex power-supply system and excessive amount of level shifters... View full abstract»

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  • Synthesis and Optimization of Pipelined Packet Processors

    Publication Year: 2009, Page(s):231 - 244
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (602 KB) | HTML iconHTML

    We consider pipelined architectures of packet processors consisting of a sequence of simple packet-processing modules interconnected by first-in first-out buffers. We propose a new model for describing their function, an automated synthesis technique that generates efficient hardware for them, and an algorithm for computing minimum buffer sizes that allow such pipelines to achieve their maximum th... View full abstract»

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  • Timing-Aware Multiple-Delay-Fault Diagnosis

    Publication Year: 2009, Page(s):245 - 258
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that those errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay-fault diagnosis problem and propose a novel approach to solve it. We enhance the diagnostic resolution by processing failure logs at various slower-than-nominal cl... View full abstract»

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  • Deviation-Based LFSR Reseeding for Test-Data Compression

    Publication Year: 2009, Page(s):259 - 271
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1812 KB) | HTML iconHTML

    Linear feedback shift register (LFSR) reseeding forms the basis for many test-compression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSR-reseeding-based compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmo... View full abstract»

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  • Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging

    Publication Year: 2009, Page(s):272 - 284
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (654 KB) | HTML iconHTML

    When hardware description languages (HDLs) are used in describing the behavior of a digital circuit, design errors (or bugs) almost inevitably appear in the HDL code of the circuit. Existing approaches attempt to reduce efforts involved in this debugging process by extracting a reduced set of error candidates. However, the derived set can still contain many error candidates, and finding true desig... View full abstract»

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  • Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug

    Publication Year: 2009, Page(s):285 - 297
    Cited by:  Papers (44)  |  Patents (64)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB) | HTML iconHTML

    To locate and correct design errors that escape pre-silicon verification, silicon debug has become a necessary step in the implementation flow of digital integrated circuits. Embedded logic analysis, which employs on-chip storage units to acquire data in real time from the internal signals of the circuit-under-debug, has emerged as a powerful technique for improving observability during in-system ... View full abstract»

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  • Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test

    Publication Year: 2009, Page(s):298 - 302
    Cited by:  Papers (11)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (313 KB) | HTML iconHTML

    Scan chain partitioning techniques are quite effective in reducing test power, as the rippling in the clock network, scan chains, and logic is reduced altogether. Partitioning approaches implemented in a static manner may fail to reduce peak power down to the desired level, however, depending on the transition distribution of the problematic pattern in the statically constructed scan chain partiti... View full abstract»

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2009, Page(s): 303
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    Publication Year: 2009, Page(s): 304
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2009, Page(s): C3
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  • Blank page [back cover]

    Publication Year: 2009, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu