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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 1 • Date Jan. 2009

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Displaying Results 1 - 23 of 23
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Page(s): C2
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  • Construction of Lossless Ladder Networks With Simple Lumped Elements Connected Via Commensurate Transmission Lines

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (435 KB) |  | HTML iconHTML  

    In this work, an algorithm to design lossless ladder networks with simple lumped elements connected via commensurate transmission lines is proposed. After giving the algorithm, a lumped-element low-pass Chebyshev filter was transformed to its mixed-element counterpart to illustrate the utilization of the algorithm. The filter, designed for a frequency band around 1 GHz, was fabricated and experimentally characterized. We find very good agreement between measured and simulated transducer power gain over the entire frequency band of interest. View full abstract»

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  • A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18- {\rm \mu}\hbox {m} CMOS Technology

    Page(s): 6 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1144 KB) |  | HTML iconHTML  

    With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is implemented in a digital 0.18-mum CMOS technology. The outputs of the PD have much wider pulse than those of the conventional linear PDs. Thus, the design of circuits such as the PD and charge becomes much easier, and the maximum data rate is no longer limited by the speed of phase detection. The CDR shows 6.8-ps rms and 57.4-ps peak-to-peak jitter in the recovered clock and 10-12 bit error rate for 231-1 pseudorandom binary-sequence input while consuming 144 mW from a 1.8-V supply. View full abstract»

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  • CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

    Page(s): 11 - 15
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB) |  | HTML iconHTML  

    A CMOS charge pump based on a transfer blocking technique and a modified precharge scheme is proposed for avoiding reversion loss and relaxing the timing restrictions imposed on input clocks. Comparison results in an 80-nm CMOS process indicate that, with no loading current, the output voltage of the proposed charge pump reaches almost 98% of the ideal boosting level with switching ripple reduced by up to 97%. They also indicate that output voltage deviations due to temperature and process variations are reduced by 24%-98% and 81%-95%, respectively. View full abstract»

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  • A 1.2-MHz 10-bit Continuous-Time Sigma–Delta ADC Using a Time Encoding Quantizer

    Page(s): 16 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (702 KB) |  | HTML iconHTML  

    This paper shows the operating principle and experimental results of a new continuous-time sigma-delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-mum CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator. View full abstract»

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  • A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock

    Page(s): 21 - 25
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1009 KB) |  | HTML iconHTML  

    A delay-locked-loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13-mum CMOS technology. The proposed clock generator can generate a wide range of the multiplied clock signals ranging from 125 MHz to 2 GHz. In addition, owing to the proposed antiharmonic-lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019 mm2 and consumes 21 mW at 2 GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones. View full abstract»

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  • Switching Schemes for Reducing Capacitor Mismatch Sensitivity of Quasi-Passive Cyclic DAC

    Page(s): 26 - 30
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (569 KB) |  | HTML iconHTML  

    An alternately complementary switching is proposed to reduce the quasi-passive cyclic DAC error caused by capacitor mismatch, and a hybrid switching is adopted to further enhance its accuracy. With 1.1% moderate capacitor mismatch, the achievable effective number of bits is as high as 15. It is shown that a three-fold improvement in accuracy can be fulfilled by the proposed hybrid switching. Since the DAC owns better immunity to process variations, smaller capacitors can be utilized to diminish both chip cost and power consumption. View full abstract»

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  • On the Computational Complexity of Tile Set Synthesis for DNA Self-Assembly

    Page(s): 31 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (285 KB) |  | HTML iconHTML  

    DNA self-assembly has been advocated as a bottom-up manufacturing technology to supersede photolithography technology at nanometer scale. However, the issue of designing a DNA tile set for an arbitrary target pattern of finite size (as to ensure periodic repetition in its assembly) has not been fully addressed in the technical literature. This paper considers the synthesis of tile sets for DNA self-assembly and analyzes it as a combinatorial optimization problem to establish its computational complexity. This problem is referred to as PATS (pattern assembling tile-set synthesis). A proof is provided for the NP-completeness of PATS. View full abstract»

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  • Self-Biased Unity-Gain Buffers With Low Gain Error

    Page(s): 36 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (783 KB) |  | HTML iconHTML  

    This paper describes self-biased unity-gain buffers that use cascaded, complementary source followers with feed forward and feedback to reduce input-output offset and gain error. Single-ended and differential buffers have been designed, fabricated and tested. View full abstract»

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  • Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques

    Page(s): 41 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (939 KB) |  | HTML iconHTML  

    A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementations, is presented. By means of a capacitive divider, the ac component of the drain-to-source voltage scaled with a factor alpha les 1 is added to the gate-to-source voltage leading to a cancellation of the nonlinear terms. The effect of alpha on resistor linearity is analytically studied. Simulation results are also provided for different technologies. Finally, a complete transconductor has been built which preserves the linearity of the MOS resistor. Three versions of the transconductor have been fabricated for different values of alpha (alpha = 0, 0.5, and 1) in a 0.5 mum CMOS technology with plusmn1.65-V supply voltage. Experimental results show (for alpha = 1 ) a THD of - 57 dB (HD2=-70 dB) at 1 MHz for 2-V peak-to-peak differential input signal with a nominal ac-transconductance of 200 muA/V and a power consumption of 3.2 mW. View full abstract»

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  • A Generalization of a Fast RNS Conversion for a New 4-Modulus Base

    Page(s): 46 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (199 KB) |  | HTML iconHTML  

    A generalization of a new generic 4-modulus base for residue number systems (RNS) is presented in this paper. An efficient RNS to binary conversion algorithm and a hierarchical architecture for these bases are also described. The key features of our conversion architecture compared to previous published architectures of the same output range are a larger moduli set selection and savings on the critical delay, area and power. The FPGA implementation and the detailed proof supporting it are also discussed. View full abstract»

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  • A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images

    Page(s): 51 - 55
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1429 KB) |  | HTML iconHTML  

    Wide-angle cameras are widely used in surveillance and medical imaging applications nowadays. Images captured by wide-angle lens suffer from barrel distortion which means that the outer regions of the image are compressed more than the inner one. A low-cost high-speed VLSI implementation for barrel distortion correction is presented in this brief. In our simulation, the proposed circuit can achieve 200 MHz with 45 K gate counts by using TSMC 0.18 mum technology. Compared with the previous distortion correction design, our circuit requires less hardware cost and achieves faster working speed. View full abstract»

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  • Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults

    Page(s): 56 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (637 KB) |  | HTML iconHTML  

    The effect of crosstalk-induced errors becomes more significant in high-performance circuits and systems. In this paper, compact crosstalk test patterns are introduced for a system-on-a-chip and board level interconnects considering physically effective aggressors. By being able to target multiple victim lines, 6n, where n is the number of nets patterns are drastically reduced to a constant number 6D, where D indicates the effective distance among interconnect nets. The test quality for static and crosstalk faults are completely preserved with 6D patterns. View full abstract»

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  • Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation

    Page(s): 61 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (225 KB) |  | HTML iconHTML  

    This paper presents two area-efficient algorithms and their architectures based on CORDIC. While the first algorithm eliminates ROM and requires only low-complexity barrel shifters, the second eliminates barrel shifters completely. As a consequence, both the algorithms consume approximately 50% area in comparison with other CORDIC designs. Further, the proposed algorithms are applicable to the entire range of angles. The FPGA implementations consume approximately 8% LUTs of a Xilinx Spartan XC2S200E device and have a slice-delay product of about 3. Convergence proofs for the algorithms are presented. Experimental comparisons with prior CORDIC designs confirm the efficacy of the proposed designs. View full abstract»

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  • Local Robustness of Hopf Bifurcation Stabilization

    Page(s): 66 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB) |  | HTML iconHTML  

    Local robust analysis via L 2 gain method is presented for a class of Hopf bifurcation stabilizing controllers. In particular, we first construct a family of Lyapunov functions for the corresponding critical system, then derive a sufficient condition to compute the L 2 gain by solving the Hamilton-Jacobi-Bellman (HJB) inequalities. Local robust analysis can be conducted through computing the local L 2 gain achieved by the stabilizing controllers at the critical situation. The theoretical results obtained in this brief provide useful guidance for selecting a robust controller from a given class of stabilizing controllers under Hopf bifurcation. As an example, application to a modified Van der Pol oscillator is discussed in details. View full abstract»

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  • Filtering for Networked Stochastic Time-Delay Systems With Sector Nonlinearity

    Page(s): 71 - 75
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB) |  | HTML iconHTML  

    This paper is concerned with the filtering problem for a class of discrete-time stochastic nonlinear networked control systems with network-induced incomplete measurements. The incomplete measurements include both the multiple random communication delays and random packet losses, which are modeled by a unified stochastic expression in terms of a set of indicator functions that is dependent on certain stochastic variable. The nonlinear functions are assumed to satisfy the sector nonlinearities. The purpose of the addressed filtering problem is to design a linear filter such that the filtering-error dynamics is exponentially mean-square stable. By using the linear-matrix-inequality (LMI) method and delay-dependent technique, sufficient conditions are derived which are dependent on the occurrence probability of both the random communication delays and missing measurement. The filter gain is then characterized by the solution to a set of LMIs. A simulation example is exploited to demonstrate the effectiveness of the proposed design procedures. View full abstract»

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  • Stabilization of Bilinear Systems Via Linear State-Feedback Control

    Page(s): 76 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB) |  | HTML iconHTML  

    This paper deals with the problem of stabilizing a bilinear system via linear state-feedback control. The proposed procedures enable us to compute a static state-feedback controller such that the zero-equilibrium point of the closed-loop system is asymptotically stable; moreover, it ensure that an assigned polytopic region is enclosed into the domain of attraction of the equilibrium point. The controller design requires the solution of a convex optimization problem involving linear matrix inequalities. The applicability of the technique is illustrated through an example, dealing with the design of a controller for a Cuk dc-dc converter. View full abstract»

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  • Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes

    Page(s): 81 - 85
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (554 KB) |  | HTML iconHTML  

    Nonbinary turbo codes have many advantages over single-binary turbo codes, but their decoder implementations require much more memory, particularly for storing symbolic extrinsic information to be exchanged between two soft-input-soft-output (SISO) decoders. To reduce the memory size required for double-binary turbo decoding, this paper presents a new method to convert symbolic extrinsic information to bit-level information and vice versa. By exchanging bit-level extrinsic information, the number of extrinsic information values to be exchanged in double-binary turbo decoding is reduced to the same amount as that in single-binary turbo decoding. A double-binary turbo decoder is designed for the WiMAX standard to verify the proposed method, which reduces the total memory size by 20%. View full abstract»

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  • Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation

    Page(s): 86 - 90
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (418 KB) |  | HTML iconHTML  

    We present a low-area implementation of an I/Q mismatch compensation (IQMC) circuit that comprises a correction engine and an adaptation engine. The correction engine performs I/Q mismatch compensation in the data path using a filter whose coefficients are updated after a programmable amount of time by a parallel adaptation engine that performs sample-by-sample off-line adaptation. This scheme allows very fast online adaptation while protecting the receiver data path from the degradations caused by a fast converging algorithm. The proposed scheme has been successfully implemented in 90-nm digital CMOS process for a low-IF quad-band GSM transceiver SoC. A single multiplier is used to perform complex multiplications for both correction and adaptation engines, resulting in a 0.025 mm2 circuit. Image Rejection Ratio in excess of 50 dB is measured that is sufficient for IF frequencies as high as 200 kHz for GSM application. View full abstract»

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  • IEEE copyright form

    Page(s): 91 - 92
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  • IEEE Circuits and Systems Society Information

    Page(s): C3
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope