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Electron Device Letters, IEEE

Issue 1 • Date Jan. 2009

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Displaying Results 1 - 25 of 37
  • Table of contents

    Publication Year: 2009 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Electron Device Letters publication information

    Publication Year: 2009 , Page(s): C2
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  • What is in a page charge?

    Publication Year: 2009 , Page(s): 1
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  • Electrical Properties of \hbox {Ga}_{2}\hbox {O}_{3}/ \hbox {GaAs} Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs

    Publication Year: 2009 , Page(s): 2 - 4
    Cited by:  Papers (21)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (347 KB) |  | HTML iconHTML  

    Electrical properties of Ga2O3/GaAs interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm (0.9 les EOT les 3.9 nm) have been characterized by capacitance-voltage measurements. Midgap interface state density Dit, effective workfunction phim, fixed charge Qf, dielectric constant kappa, and low field leakage current density are 2 times1011 cm-2 middoteV-1, 4.93 eV, -8.9 times1011 cm-2, 19.5, and 10-9- 10-8 A/cm2, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation. View full abstract»

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  • High-Performance \hbox {In}_{0.7}\hbox {Ga}_{0.3}\hbox {As} -Channel MOSFETs With High- \kappa Gate Dielectrics and \alpha -Si Passivation

    Publication Year: 2009 , Page(s): 5 - 7
    Cited by:  Papers (41)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (365 KB) |  | HTML iconHTML  

    Long and short buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated. Devices with alpha-Si passivation show much higher transconductance and an effective peak mobility of 3810 cm2/ V middots. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 muA/mum at Vg - Vt = 1.6 V and peak transconductance of 715 muS/mum. In addition, the virtual source velocity extracted from the short-channel devices is 1.4-1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance In0.7Ga0.3 As-channel MOSFETs passivated by an alpha -Si layer are promising candidates for advanced post-Si CMOS applications. View full abstract»

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  • A Nonvolatile Memory With Resistively Switching Methyl-Silsesquioxane

    Publication Year: 2009 , Page(s): 8 - 10
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    Crossbar structures with integrated methyl-silsesquioxane (MSQ) were fabricated by UV nanoimprint lithography. The sandwiched MSQ film was used for the planarization of the bottom electrodes' interface as well as for the realization of functional resistively switching crosspoint junctions. With our process, future nonvolatile crossbar memories with stacking and, thus, high integration density potential can be realized. Using MSQ as functional material additionally indicates an attractive opportunity because it is highly CMOS compatible. By programming word registers with different bit patterns, we demonstrate the potential of this crossbar architecture for future memory and logic applications. View full abstract»

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  • Delamination and Electromigration of Film Lines on Polymer Substrate Under Electrical Loading

    Publication Year: 2009 , Page(s): 11 - 13
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (281 KB) |  | HTML iconHTML  

    As the main influencing factors for instability of film lines are widely used in microelectromechanical systems, buckle-driven delamination and electromigration of film lines on polymer substrate under electrical loading are reported in this letter. The critical buckling condition is obtained through Euler formula. In addition, postbuckling analysis for the film is derived to calculate the residual stress distribution. Both electromigration and buckling stress control the film fracture. Film buckling depends not only on the thermal mismatch between the film line and the substrate but also on the applied electrical loading. View full abstract»

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  • Design and Fabrication of Stretchable Multilayer Self-Aligned Interconnects for Flexible Electronics and Large-Area Sensor Arrays Using Excimer Laser Photoablation

    Publication Year: 2009 , Page(s): 14 - 17
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (458 KB)  

    Stretchable interconnects are fabricated on polymer substrates using metal patterns both as functional interconnect layers and as in situ masks for excimer laser photoablation. Single-layer and multilayer interconnects of various designs (rectilinear and ldquomeanderingrdquo) have been fabricated, and certain ldquomeanderingrdquo interconnect designs can be stretched up to 50% uniaxially while maintaining good electrical conductivity and structural integrity. This approach eliminates masks and microfabrication processing steps as compared to traditional fabrication approaches. Furthermore, this technology is scalable for large-area sensor arrays and electronic circuits, adaptable for a variety of materials and interconnects designs, and compatible with MEMS-based capacitive sensor technology. View full abstract»

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  • Design and Fabrication of Stretchable Multilayer Self-Aligned Interconnects for Flexible Electronics and Large-Area Sensor Arrays Using Excimer Laser Photoablation

    Publication Year: 2009 , Page(s): 14 - 17
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (455 KB)  

    Stretchable interconnects are fabricated on polymer substrates using metal patterns both as functional interconnect layers and as in situ masks for excimer laser photoablation. Single-layer and multilayer interconnects of various designs (rectilinear and “meandering”) have been fabricated, and certain “meandering” interconnect designs can be stretched up to 50% uniaxially while maintaining good electrical conductivity and structural integrity. This approach eliminates masks and microfabrication processing steps as compared to traditional fabrication approaches. Furthermore, this technology is scalable for large-area sensor arrays and electronic circuits, adaptable for a variety of materials and interconnects designs, and compatible with MEMS-based capacitive sensor technology. View full abstract»

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  • A UV-Erasable Stacked Diode-Switch Organic Nonvolatile Bistable Memory on Plastic Substrates

    Publication Year: 2009 , Page(s): 18 - 20
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (387 KB) |  | HTML iconHTML  

    In this letter, we demonstrate a robust and stacked diode-switch organic nonvolatile bistable memory (DS-ONBM) using polymer-chain-stabilized gold nanoparticles on a plastic substrate in ambient air. The absorption spectrum of the gold nanoparticles shows ultraviolet (UV) absorption. Therefore, UV light is used to erase data in the DS-ONBM. The data in the memory can be retained for more than ten days in the air. The estimated retention time is nearly a year. This DS-ONBM is demonstrated to read, write, and retain the data and is reusable by UV-light illumination. Hence, the UV-erasable DS-ONBM is fully applicable in printed electronics such as RFID tags. View full abstract»

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  • Near-Ballistic Unitraveling-Carrier Photodiode-Based V-band Optoelectronic Mixers With Low Upconversion Loss and High Operation Current Performance Under Optical IF Signal Injection

    Publication Year: 2009 , Page(s): 21 - 23
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB) |  | HTML iconHTML  

    We demonstrate near-ballistic unitraveling-carrier photodiode (NBUTC-PD)-based V-band (50-75 GHz) optoelectronic (OE) mixers which can upconvert the V-band optical local-oscillator (LO) and intermediate-frequency (IF) signals. The optical LO and IF signals share a single erbium-doped optical fiber amplifier (EDFA) which means that the mixing performance of the device can be optimized by properly adjusting the ratio between the injected optical LO and IF power to the EDFA. The utilization of the strong nonlinearity of the ballistic transport of the electrons in the NBUTC-PD under a reverse bias regime means that our device achieves a low upconversion loss ( -6 dB) under a very high operating current (23 mA) in V-band (60 GHz). We are able to improve the operating current at the V-band over that previously reported for UTC-PD-based OE mixers. This is made possible by an increase in the optimum operating voltage from the near forward bias (0 V) to the reverse bias regime (-1.7 V). View full abstract»

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  • Experimental Determination of the Gain Distribution of an Avalanche Photodiode at Low Gains

    Publication Year: 2009 , Page(s): 24 - 26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (153 KB) |  | HTML iconHTML  

    A measurement system for determining the gain distributions of avalanche photodiodes (APDs) in a low gain range is presented. The system is based on an ultralow-noise charge-sensitive amplifier and detects the output carriers from an APD. The noise of the charge-sensitive amplifier is as low as 4.2 electrons at a sampling rate of 200 Hz. The gain distribution of a commercial Si APD with low average gains is presented, demonstrating the McIntyre theory in the low gain range. View full abstract»

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  • High 366/254-nm Rejection Contrast GaN MIS Photodetectors Using Nano Spin-Oxide

    Publication Year: 2009 , Page(s): 27 - 29
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (273 KB) |  | HTML iconHTML  

    In this paper, GaN-based metal-insulator-semiconductor (MIS) photodetectors (PDs) with liquid-phase deposition oxide (LPD oxide) or nanospin oxide were fabricated and compared. Compared to the MIS-PDs with LPD oxide, the nanospin-oxide device can dramatically reduce the optical response of 254 nm by two orders while still retaining the same 366-nm optical response as LPD oxide. The 366/254-nm rejection contrast is raised from 5.13 to 413 for the MIS-PDs with LPD and spin oxides, respectively. Thus, one can simply insert a thin (10 nm) nanospin-oxide layer between the metal and GaN to significantly reduce the response of 254 nm. Possible mechanism is discussed here. View full abstract»

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  • Dual Gate ZnO-Based Thin-Film Transistors Operating at 5 V: nor Gate Application

    Publication Year: 2009 , Page(s): 30 - 32
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (429 KB) |  | HTML iconHTML  

    We report on the fabrication of ZnO-based dual gate (DG) thin-film transistors (TFTs) with 20-nm-thick Al2O3 for both top and bottom dielectrics, which were deposited by atomic layer deposition on glass substrates at 200 degC. As characterized with single gate (SG), DG, and ground plane (GP) modes, our ZnO TFTs are well operated under 5 V. DG-mode TFT showed a field mobility of 0.38 cm2/V middots, a high saturation current of 6 muA, and an on/off current ratio of ~ 106, while SG- and GP-mode TFTs showed a similar value of mobility but with lower current. Using DG and GP modes, nor gate operation was well demonstrated. View full abstract»

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  • A Reduced Mask-Count Technology for Complementary Polycrystalline Silicon Thin-Film Transistors With Self-Aligned Metal Electrodes

    Publication Year: 2009 , Page(s): 33 - 35
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    The inexpensive glass substrate for building conventional low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) imposes a ceiling on the TFT processing temperature. This results in a reduced efficiency of dopant activation and a high source/drain series resistance. A technique based on aluminum-induced crystallization of amorphous silicon has been applied to fabricate TFTs with low-resistance self-aligned metal electrodes (SAMEs). While at least two masked implantation steps are typically used for constructing the doped source and drain regions of conventional n- and p-channel TFTs in a complementary metal-oxide-semiconductor circuit technology, it is currently demonstrated that complementary SAME poly-Si TFTs can be constructed using a combination of a masked and a blanket source and drain implantation steps. The decrease in mask count reduces process complexity and cost. Control of ion channeling is the enabling factor behind the successful demonstration of the technology. View full abstract»

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  • A Center-Offset Polycrystalline-Silicon Thin-Film Transistor With {\rm n}^{+} Amorphous-Silicon Contacts

    Publication Year: 2009 , Page(s): 36 - 38
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (477 KB) |  | HTML iconHTML  

    We have studied a bottom-gate polycrystalline-silicon thin-film transistor (poly-Si TFT) with amorphous-silicon (a-Si) n+ contacts and center-offset gated structure, where intrinsic poly-Si is used in the center-offset region. The fabrication process is compatible with the conventional a-Si TFT with addition of thermal annealing for crystallization of a-Si. The bottom-gate poly-Si TFT with a 5-mum offset length exhibited a field-effect mobility of 18.3 cm2/V middots and minimum OFF-state current of 2.79 times 10-12A/mum at Vds= 5 V. The leakage currents are two orders of magnitude lower than those of a nonoffset TFT with mobility drop from 23.8 to 18.3 cm2/ Vmiddots. View full abstract»

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  • High-Performance Poly-Silicon TFTs Using a High- k \hbox {PrTiO}_{3} Gate Dielectric

    Publication Year: 2009 , Page(s): 39 - 41
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (374 KB) |  | HTML iconHTML  

    In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high-k PrTiO3 gate dielectric is proposed for the first time. Compared to TFTs with a Pr2O3 gate dielectric, the electrical characteristics of poly-Si TFTs with a PrTiO3 gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher I on/I off current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high-k PrTiO3 gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays. View full abstract»

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  • A Novel Five-Photo-Mask Low-Temperature Polycrystalline-Silicon CMOS Structure With Improved Contact Resistance

    Publication Year: 2009 , Page(s): 42 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (295 KB) |  | HTML iconHTML  

    In this letter, a novel five-mask low-temperature polycrystalline-silicon (LTPS) complementary metal-oxide-semiconductor (CMOS) structure was proposed to improve cost competitiveness of CMOS products on the market and was verified by manufacturing test samples using the five-mask LTPS CMOS process. Selective contact-barrier-metal formation process was first introduced to solve the high-contact-resistance problem encountered between indium-tin-oxide and doped poly-Si source/drain. The five-mask CMOS devices showed comparable device performances to CMOS devices with conventional structure, i.e., 1.32 V of threshold voltage and 267.6 cm2/Vmiddots of maximum field-effect mobility for NMOS, and those of -1.24 V and 125.2 cm2/Vmiddots for PMOS, respectively. View full abstract»

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  • Self-Stabilization in Amorphous Silicon Circuits

    Publication Year: 2009 , Page(s): 45 - 47
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB) |  | HTML iconHTML  

    Thin-film transistors (TFTs) based on disordered semiconductors such as amorphous hydrogenated silicon (a-Si:H) experience a threshold voltage (VT) shift with time in the presence of a gate bias. The VT shift needs to be compensated for circuit applications. We study an interesting property of self-compensation in fundamental analog TFT circuits with one a part of the circuit compensating for the effects of VT shift in the other and vice versa. View full abstract»

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  • Transparent Oxide Thin-Film Transistors Composed of Al and Sn-doped Zinc Indium Oxide

    Publication Year: 2009 , Page(s): 48 - 50
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    We have fabricated the transparent bottom gate thin-film transistors (TFTs) using Al and Sn-doped zinc indium oxide (AT-ZIO) as an active layer. The AT-ZIO active layer was deposited by RF magnetron sputtering at room temperature, and the AT-ZIO TFT showed a field effect mobility of 15.6 cm2/Vs even before annealing. The mobility increased with increasing the In2O3 content and postannealing temperature up to 250degC. The AT-ZIO TFT exhibited a field effect mobility of 30.2 cm2/Vs, a subthreshold swing of 0.17 V/dec, and an on/off current ratio of more than 109 . View full abstract»

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  • Robustness of SiC JFET in Short-Circuit Modes

    Publication Year: 2009 , Page(s): 51 - 53
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (678 KB) |  | HTML iconHTML  

    This letter presents first destructive results showing the robustness of SiC JFET transistors from SiCED in current limitation regime or short-circuit operation. Crystal temperature during failure was estimated after different electrical characterizations and using appropriate models of saturation current. This letter shows the exceptional robustness of SiC JFET transistors in current limitation mode compared to Si devices (MOSFETS and IGBTs). View full abstract»

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  • New Hot-Carrier Injection Mechanism at Source Side in Nanoscale Floating-Body MOSFETs

    Publication Year: 2009 , Page(s): 54 - 56
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (435 KB) |  | HTML iconHTML  

    A new hot-carrier injection mechanism that depends on gate bias and body thickness in nanoscale floating-body MOSFETs has been identified using 2-D device simulation and hot-carrier degradation measurements. When gate voltage is sufficiently high and the body thickness is thin, the potential of the floating body is elevated due to the ohmic voltage drop at the source extension (SE), resulting in impact ionization at the SE. Hot-carrier stress with accelerated gate voltage may lead to a huge overestimation of lifetime in nanoscale floating-body MOSFETs. View full abstract»

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  • Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs

    Publication Year: 2009 , Page(s): 57 - 60
    Cited by:  Papers (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    Low-frequency noise (LFN) in n-type silicon nanowire MOSFETs (SNWTs) is investigated in this letter. The drain-current spectral density exhibits significant dispersion of up to five orders of magnitude due to the ultrasmall dimensions of SNWTs. The measured results show that LFN in SNWTs can be well described by the correlated-mobility fluctuation model at low drain current, with the effective oxide trap density extracted and discussed. At high drain current, however, the input-referred noise spectral density increases rapidly with the drain current, which indicates the significant impact of the ultranarrow source/drain extension regions of SNWTs. As a result, design optimizations to reduce the impact of parasitic resistance in SNWTs are necessary for analog/RF applications. View full abstract»

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  • Enhanced Electrical and Thermal Properties of Trench Metal–Oxide–Semiconductor Field-Effect Transistor Built on Copper Substrate

    Publication Year: 2009 , Page(s): 61 - 63
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    Vertical metal-oxide-semiconductor field-effect transistors (UMOSFETs) were built on silicon substrates thinned to 7 mum and plated with 50- mum copper as drain electrode and mechanical support. Compared to the same devices on silicon substrates of 200 mum thick, the UMOSFET on 7-mum silicon demonstrates at least 16% less channel resistance and two times better device ruggedness. The reduced resistance is due to enhanced carrier mobility caused by increasing biaxial compressive thermal stress in silicon perpendicular to the channel, which is confirmed by a 3-D piezoresistance model. The doubling of ruggedness is attributed to a much improved transient thermal conductance. View full abstract»

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  • A Novel Depletion-IMOS (DIMOS) Device With Improved Reliability and Reduced Operating Voltage

    Publication Year: 2009 , Page(s): 64 - 67
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB) |  | HTML iconHTML  

    We experimentally demonstrate a novel depletion-IMOS (DIMOS) device with a 12.1-mV/dec subthreshold slope and 5-decade ON/OFF ratio, employing a depletion mode of operation instead of inversion. DIMOS structure improves reliability by reducing hot carrier injection and features 40% lower breakdown voltages with higher ON currents compared to conventional IMOS. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Editor-in-Chief

Amitava Chatterjee