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Electrical and Computer Engineering, Canadian Journal of

Issue 3/4 • Date Summer-Fall 2008

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Displaying Results 1 - 16 of 16
  • Canadian Journal of Electrical and Computer Engineering - Front cover

    Publication Year: 2008 , Page(s): c1 - c4
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    Freely Available from IEEE
  • Canadian Journal of Electrical and Computer Engineering - Table of contents

    Publication Year: 2008 , Page(s): i - ii
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    Freely Available from IEEE
  • IEEE Canadian Conference on Electrical and Computer Engineering 2008

    Publication Year: 2008 , Page(s): iii - iv
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    Freely Available from IEEE
  • A new design tool to protect industrial long-cable PWM ASD systems against high-frequency overvoltage problems

    Publication Year: 2008 , Page(s): 125 - 132
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    This work presents a new tool for use in the design of long-cable adjustable-speed drive (ASD) systems. It allows coordination between the inverter, the motor and the cable type and length in order to protect the motor against overvoltages due to the reflected wave. Detailed mathematical formulas describing the transient voltage and current along the cable are first developed in the frequency domain. Then, by applying the boundary conditions at the cable ends and assuming a lossless cable, delay equations are developed in the time domain. Using these equations, an appropriate simulation scheme is built with the SimPowerSystems (SPS) and Simulink modules of the MATLAB software environment to compute the high-frequency overvoltages (and their associated currents) at the ends of the feeding cable. The proposed tool has been applied to a 5 kVA industrial ASD prototype using a four-wire shielded long cable. The paper includes simulation results and experimental validations. View full abstract»

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  • Multiple description coding by successive quantization

    Publication Year: 2008 , Page(s): 133 - 138
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    Two structured multiple description (MD) vector quantization schemes with an iterative technique for designing the codebooks and partitions are proposed. The schemes are derived from the recent theoretical work by Chen et al. In the first scheme, the central decoder is formed by the weighted sum of the side codebooks, whereas the second scheme employs the optimum central decoder. The objective of the proposed iterative method is to minimize a Lagrangian cost function (defined as the weighted sum of the central and side distortions) to jointly design the side codebooks and find the associated partitions. The optimal parameters for minimizing the central distortion are also found. Simulations demonstrate that the proposed methods achieve performance close to that of the unstructured, full-search MD quantizer with considerably less complexity and with only a few iterations. View full abstract»

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  • Selenium-based amorphous silicon flat-panel digital X-ray imager for protein crystallography

    Publication Year: 2008 , Page(s): 139 - 143
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    This work proposes a large-area detector for protein crystallography based on an amorphous silicon (a-Si:H) thin film transistor (TFT) pixel-array backplane and an overlying amorphous selenium (a-Se) photoconductor for direct conversion of incident X-rays into an image charge. To achieve high sensitivity, avalanche multiplication in a-Se is adopted to make the detector sensitive to each incident X-ray. The use of a-Si:H technology enables large-area imaging of protein diffraction patterns at less expense compared to existing charge coupled device (CCD) and imaging plate (IP) detectors. In addition, a theoretical analysis shows that the detector exhibits fast readout speed (readout time <1 s), high dynamic range (~106), high sensitivity (~1 X-ray photon), and high detective quantum efficiency (~0.7), thus validating its suitability for protein crystallography. View full abstract»

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  • Cooperative hybrid multi-camera tracking for people surveillance

    Publication Year: 2008 , Page(s): 145 - 152
    Cited by:  Papers (7)
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    In this paper, a novel hybrid visual tracking system for event detection and people tracking is proposed. This surveillance system is composed of a stationary camera and a pan/tilt/zoom (PTZ) camera. The stationary camera has a wide field of view and detects fall and wandering events by means of motion-based visual tracking. The PTZ camera then tracks and follows the person who triggered an event using colour-based particle filtering. The purpose of tracking in view of the PTZ camera is to continuously keep the person in the camera view in order to obtain identifying details. Experimental results for event detection and people tracking are presented to demonstrate the proposed cooperative hybrid visual tracking system. View full abstract»

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  • Novel dual auxiliary circuits for ZVT-PWM converters

    Publication Year: 2008 , Page(s): 153 - 160
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1231 KB)  

    Novel active auxiliary circuits that allow the power switch in single-switch, pulse-width-modulated (PWM) converters to operate with zero-voltage switching (ZVS) are proposed in this paper. The main feature of these circuits is that the auxiliary switch can operate with a zero-current switching turn-on and turn-off without increasing the peak current stresses of the main switch. In this paper, the operation of active auxiliary circuits in general is reviewed, and a systematic method for synthesizing auxiliary circuits belonging to the new family is presented and demonstrated with several examples. Several new auxiliary circuits are presented, and the operation of one of the new circuits is briefly explained. A general set of guidelines for the design of auxiliary circuits belonging to the new family is presented. The feasibility of the new family of circuits is confirmed by experimental results obtained from a 500 W, 100 kHz zero-voltage-transition (ZVT)-PWM boost converter prototype implemented with an example auxiliary circuit. View full abstract»

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  • All-optical processing using light intensity and wavelength recognition

    Publication Year: 2008 , Page(s): 161 - 168
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (901 KB)  

    A simple multi-valued processing logic relying on two basic operations, namely, addition and comparison, is presented. These two basic operations have minimal switching levels, since the addition operation is performed without switches and the comparison operation is performed with only one switch. A simplified illustrative model of a system based on this logic is also presented. The paper includes a limited survey of optical components that can be used in the presented system. View full abstract»

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  • Design tradeoff analysis of floating-point adders in FPGAs

    Publication Year: 2008 , Page(s): 169 - 175
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    With gate counts of ten million, field-programmable gate arrays (FPGAs) are becoming suitable for floating-point computations. Addition is the most complex operation in a floating-point unit and can cause major delay while requiring a significant area. Over the years, the VLSI community has developed many floating-point adder algorithms aimed primarily at reducing the overall latency. An efficient design of the floating-point adder offers major area and performance improvements for FPGAs. Given recent advances in FPGA architecture and area density, latency has become the main focus in attempts to improve performance. This paper studies the implementation of standard; leading-one predictor (LOP); and far and close datapath (2-path) floating-point addition algorithms in FPGAs. Each algorithm has complex sub-operations which contribute significantly to the overall latency of the design. Each of the sub-operations is researched for different implementations and is then synthesized onto a Xilinx Virtex-II Pro FPGA device. Standard and LOP algorithms are also pipelined into five stages and compared with the Xilinx IP. According to the results, the standard algorithm is the best implementation with respect to area, but has a large overall latency of 27.059 ns while occupying 541 slices. The LOP algorithm reduces latency by 6.5% at the cost of a 38% increase in area compared to the standard algorithm. The 2-path implementation shows a 19% reduction in latency with an added expense of 88% in area compared to the standard algorithm. The five-stage standard pipeline implementation shows a 6.4% improvement in clock speed compared to the Xilinx IP with a 23% smaller area requirement. The five-stage pipelined LOP implementation shows a 22% improvement in clock speed compared to the Xilinx IP at a cost of 15% more area. View full abstract»

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  • Combining ESOP minimization with BDD-based decomposition for improved FPGA synthesis

    Publication Year: 2008 , Page(s): 177 - 182
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (743 KB)  

    This paper proposes a novel method to improve the utilization efficiency and performance of field-programmable gate arrays (FPGAs). The proposed method, ExorBDD, uses a stage of exclusive-sum-of-product (ESOP) minimization, followed by a stage of decomposition using binary decision diagrams (BDDs). For exclusive OR (XOR)-intensive circuits, experiments were conducted on 19 MCNC benchmark parity circuits (ranging from 5 to 25 inputs), as they are the most representative case of XOR-intensive circuits. The results using the proposed approach show significant improvements over Exorcism4, BDS, and commercial tools. On average, the new approach uses only 30.3% as many look-up tables as are used by Xilinx tools (and only 16.4% in comparison to Altera). On average, the new approach has a maximum combinational path delay of 89.2% compared to the delay with Xilinx tools (80.3% compared to Altera). Experiments were also conducted on non-XOR-intensive circuits. These results show that ExorBDD also performs well for arbitrary circuits. View full abstract»

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  • Fixed-switching-frequency DTC control for PM synchronous machine with minimum torque ripples

    Publication Year: 2008 , Page(s): 183 - 189
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (927 KB)  

    In this paper, fixed-frequency direct torque control (DTC) of a permanent magnet synchronous motor (PMSM) is presented. In this method, the stator voltage vector is generated according to the increase stator flux components in the stationary frame ( alpha,beta ). A control algorithm based on predictive control to reduce the effect of the computing time on the stator flux vector position is also presented. The implementation of this method in the case of a PMSM, which is done without hysteresis regulators, is simple and does not require any filter. Simulation and experimental results show that the proposed method reduces the torque ripple while achieving a good dynamic response. View full abstract»

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  • Development of an electrothermal simulation tool for integrated circuits: Application to a two-transistor circuit

    Publication Year: 2008 , Page(s): 191 - 200
    Cited by:  Papers (3)
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    In this paper a methodology for performing electrothermal analyses on integrated circuits is introduced. Using the relaxation method, standard electrical and thermal simulators, which are often used in the design process, are coupled through an efficient interface program. The simulator is capable of performing steady-state and transient analysis at device and chip levels. A variable-time-step technique has been implemented to reduce the computational time for a given set of computational resources. The simulator has been validated on different structures such as the bipolar junction transistor to predict the temperature distribution and the device performance in an amplifier circuit and an integrated current-mirror circuit. The simulation results are compared to experimental results to verify the performance of the electrothermal simulator and the accuracy of the thermal model. Simulation results demonstrate that the approach is suitable to model the thermal effects of integrated circuits in a more time-efficient, accurate and user-friendly fashion. View full abstract»

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  • Optimal routing and wavelength assignment for survivable multifibre WDM networks

    Publication Year: 2008 , Page(s): 201 - 208
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (631 KB)  

    Multifibre optical networks use a bundle of fibres to realize a link between two optical nodes. Such networks can offer significant economic benefits over single-fibre networks because of their ability to relax the restrictions imposed by the wavelength continuity constraint and their potential for handling future growth. This paper introduces two new and efficient integer linear program (ILP) formulations for dynamic wavelength allocation in survivable multifibre wavelength-division multiplexing (WDM) networks, using dedicated and shared protection. Single-fibre networks, both with and without wavelength conversion, can be treated as a special case of these formulations. The new formulations have been tested on several well-known WDM networks, and the results have been compared to those for single-fibre networks. A simple heuristic for dynamic lightpath allocation is also proposed, and its performance is validated by a comparison of the results to optimal solutions generated by the ILPs. Experimental results demonstrate that the new ILPs are feasible for current networks under low-to-medium traffic. For very large or highly congested networks, the heuristic can be used. View full abstract»

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  • A new compact dual-core architecture for AES encryption and decryption

    Publication Year: 2008 , Page(s): 209 - 213
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    This article presents a new compact architecture, consisting of two independent cores that process encryption and decryption simultaneously, for the Advanced Encryption Standard (AES) algorithm. The corresponding new compact key generation unit with 32-bit datapath is also explored to provide round keys on the fly for encryption and decryption. A novel way to implement ShiftRows/InvShiftRows, one of the key designs in the compact 32-bit architecture, is proposed. The new AES implementation requires only 16 629 gate equivalents on the 0.35 mum CMOS technology from CSMC Technologies Corporation, while providing encryption and decryption in parallel with 335 Mbits/s throughput. View full abstract»

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  • A robust algorithm for text region detection in natural scene images

    Publication Year: 2008 , Page(s): 215 - 222
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    In this paper, a new method for detecting text regions in natural scene images is presented. The proposed algorithm is based on the segmentation of objects in a scene, followed by the identification of text objects by a support vector machine (SVM). First, to segment objects in the scene, the input image is separated into chromatic and achromatic regions according to the distribution of red, green and blue (RGB) elements, and different clustering algorithms are applied. Second, each object is transformed into the wavelet domain for multi-resolution analysis, and moment features of the wavelet coefficients are used in the SVM for the classification of text objects. The proposed approach provides robustness to non-uniform illumination by using different clustering algorithms according to the characteristics of the colour components in the segmentation. Also, moment features, used for classification, are invariant to the size, direction, shape and other properties of texts. Experimental results demonstrate the effectiveness of this approach. View full abstract»

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Aims & Scope

The role of the Canadian Journal of Electrical and Computer Engineering is to provide scientific and professional activity for its members in Canada, the CJECE complements international journals and will be of particular interest to anyone involved in research and development activities in the field of electrical and computer engineering.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Dr. Shahram Yousefi
Dept. of Electrical and Computer
     Engineering
Queen's University