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# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 25 of 28
• ### Table of contents

Publication Year: 2008, Page(s):C1 - C4
| PDF (45 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2008, Page(s): C2
| PDF (39 KB)
• ### A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR

Publication Year: 2008, Page(s):1089 - 1093
Cited by:  Papers (6)
| | PDF (731 KB) | HTML

This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current-voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for com... View full abstract»

• ### A 3–8 GHz Delay-Locked Loop With Cycle Jitter Calibration

Publication Year: 2008, Page(s):1094 - 1098
Cited by:  Papers (7)
| | PDF (1073 KB) | HTML

A 3-8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitters a... View full abstract»

• ### Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs

Publication Year: 2008, Page(s):1099 - 1103
Cited by:  Papers (16)
| | PDF (236 KB) | HTML

Several design options are nowadays available for the frequency compensation of CMOS two-stage transconductance operational amplifiers, from the traditional Miller approach employing a nulling resistor or a voltage buffer, to a current buffer or the more modern current amplifier. However, designers have no results on the frequency performance achievable that allow to consciously choose the best ap... View full abstract»

• ### Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators

Publication Year: 2008, Page(s):1104 - 1108
Cited by:  Papers (17)  |  Patents (1)
| | PDF (595 KB) | HTML

In this paper, we extend the idea developed in some of our earlier works of using output feedback to make the quantization step in a digital delta-sigma modulator (DDSM) appear prime. This maximizes the cycle lengths for constant inputs, spreading the quantization error over the maximum number of frequency terms, and consequently, minimizing the power per tone. We show how this concept can be appl... View full abstract»

• ### Wideband Signal Synthesis Using Interleaved Partial-Order Hold Current-Mode Digital-to-Analog Converters

Publication Year: 2008, Page(s):1109 - 1113
Cited by:  Papers (8)  |  Patents (4)
| | PDF (316 KB) | HTML

We describe how a zero-order hold digital-to-analog converter (DAC) followed by a windowed-integration-based filter results in a novel partial-order hold (POH) DAC architecture with the ability of broadband image reduction between 1.5 and two times the sampling frequency while also providing a flat-group delay. Interleaving two such POH-DACs results in a DAC with an excellent output signal reconst... View full abstract»

• ### Performance Enhancement of Colpitts Oscillators by Parasitic Cancellation

Publication Year: 2008, Page(s):1114 - 1118
Cited by:  Papers (6)
| | PDF (377 KB) | HTML

The performance of conventional common-collector Colpitts oscillators is limited at higher frequencies due to the parasitic base-collector capacitance Cbe and the base-emitter capacitance Cbe. Due to the Miller effect, the parasitic capacitance Cbe significantly reduces the negative resistance. A large collector inductor further reduces the negative resistance. Thi... View full abstract»

• ### Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators

Publication Year: 2008, Page(s):1119 - 1123
Cited by:  Papers (32)
| | PDF (268 KB) | HTML

We present a simple, intuitive technique to compensate the loop filter transfer function for excess delay in low-pass continuous-time DeltaSigma modulators. Conventional methods of finding the appropriate filter coefficients to account for loop delay work in the z-domain, leading to cumbersome algebra. We show that the same objective can be accomplished entirely in the continuous-time domai... View full abstract»

• ### A MOSFET-Based Wide-Dynamic-Range Translinear Element

Publication Year: 2008, Page(s):1124 - 1128
Cited by:  Papers (2)
| | PDF (893 KB) | HTML

A fully CMOS-compatible translinear element that precisely follows the exponential relation between its input control voltage and output current over more than seven decades of the output current is presented. A statistical analysis of the I - V characteristic of 75 manufactured translinear elements reveals good matching behavior. The proposed translinear element has been tested as a key building ... View full abstract»

• ### A Novel Architecture of Delta-Sigma Modulator Enabling All-Digital Multiband Multistandard RF Transmitters Design

Publication Year: 2008, Page(s):1129 - 1133
Cited by:  Papers (70)  |  Patents (3)
| | PDF (486 KB) | HTML

This paper proposes a new architecture of delta-sigma (DS) modulator suitable for RF digital transmitter design. This novel architecture considerably reduces the speed requirements of the digital signal processing block. The novelty lies in the implementation of a specific fully digital up-conversion in combination with a low-pass DS modulator to produce high-frequency digital-like signals, which ... View full abstract»

• ### Optimality of Bus-Invert Coding

Publication Year: 2008, Page(s):1134 - 1138
Cited by:  Papers (3)  |  Patents (1)
| | PDF (260 KB) | HTML

Dynamic power dissipation on I/O buses is an important issue for high-speed communication between chips. One can use coding techniques to reduce the number of transitions, which will reduce the dynamic power. Bus-invert coding is one popular technique for interchip buses, where the dominant contribution is from the self-capacitance of the wires. This algorithm uses an invert line to signal whether... View full abstract»

• ### Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations

Publication Year: 2008, Page(s):1139 - 1143
Cited by:  Papers (8)
| | PDF (265 KB) | HTML

In this paper, a low latency angle recoding method for the higher bit-width parallel coordinate rotation digital computer (CORDIC) rotator implementations is proposed. In previous studies, parallel CORDIC (para-CORDIC) rotators have been used to reduce the computational bottleneck by precomputing the required rotation directions. However, the number of required microrotations increases with the bi... View full abstract»

• ### A Combined Circuit for Multiplication and Inversion in ${rm GF}(2^{m})$

Publication Year: 2008, Page(s):1144 - 1148
Cited by:  Papers (3)
| | PDF (484 KB) | HTML

A combined circuit for multiplication and inversion in GF(2m) is proposed. In order to develop a combined circuit, we start with combining the most significant bit first multiplication algorithm and the modified extended Euclid's algorithm by focusing on the similarities between them. Since almost all hardware components of the circuits are shared by multiplication and inversion, the co... View full abstract»

• ### An Efficient FFT Engine With Reduced Addressing Logic

Publication Year: 2008, Page(s):1149 - 1153
Cited by:  Papers (13)
| | PDF (354 KB) | HTML

In this study, an improved butterfly structure and an address generation method for fast Fourier transform (FFT) are presented. The proposed method uses reduced logic to generate the addresses, avoiding the parity check and barrel shifters commonly used in FFT implementations. A general methodology for radix-2 N-point transforms is derived and the signal flow graph for a 16-point FFT is presented.... View full abstract»

• ### A Least-Squares Filter Design Technique for the Compensation of Frequency Response Mismatch Errors in Time-Interleaved A/D Converters

Publication Year: 2008, Page(s):1154 - 1158
Cited by:  Papers (30)  |  Patents (3)
| | PDF (287 KB) | HTML

This paper introduces a least-squares filter design technique for the compensation of frequency response mismatch errors in M-channel time-interleaved analog-to-digital converters. The overall compensation system is designed by determining M filter impulse responses analytically through M separate matrix inversions. The proposed technique offers an alternative to least-squares techniques that dete... View full abstract»

• ### Sampling and Reconstruction of Piecewise Constant Signals by Parallel CR-Network

Publication Year: 2008, Page(s):1159 - 1162
Cited by:  Papers (1)
| | PDF (102 KB) | HTML

Piecewise constant (PWC) waveforms consisting of amplitude-modulated edges (AMEs) are an important signal family in optical communication technology. The sampling of PWC signals by an analog-to-digital converter (ADC) requires an extremely high sampling rate. In this paper, we show that PWC signals can be measured and reconstructed using a parallel capacitor-resistor network (PCRN). The reconstruc... View full abstract»

• ### A Delay-Range-Dependent Approach to Design State Estimator for Discrete-Time Recurrent Neural Networks With Interval Time-Varying Delay

Publication Year: 2008, Page(s):1163 - 1167
Cited by:  Papers (21)
| | PDF (141 KB) | HTML

This paper deals with the problem of state estimation for discrete-time recurrent neural networks with interval time-varying delay. The activation functions are assumed to be globally Lipschitz continuous. A delay-range-dependent condition for the existence of state estimators is proposed. Via available output measurements and solutions to certain linear matrix inequalities, general full-order sta... View full abstract»

• ### Generation of $ntimes m$-Wing Lorenz-Like Attractors From a Modified Shimizu–Morioka Model

Publication Year: 2008, Page(s):1168 - 1172
Cited by:  Papers (42)
| | PDF (1903 KB) | HTML

This paper explores the generation of n- and n times m-wing Lorenz-type attractors from a modified Shimizu-Morioka system. The basic idea is to increase the number of index-2 equilibrium points by introducing a multisegment quadratic function and a stair function in the 2-D state-space of the system. The design is verified by both simulation and experiment, where multiwing attractors over a grid c... View full abstract»

• ### A Simple Programmable Autowave Generator Network for Wave Computing Applications

Publication Year: 2008, Page(s):1173 - 1177
Cited by:  Papers (13)
| | PDF (134 KB) | HTML

Spatiotemporal-wave-based computing on an active medium, which is known as wave computing paradigm, mimics the way biological systems process information. Recent anatomic and physiological studies and technological developments in very large-scale integration technology have encouraged the engineers to brace up with this new paradigm. In this paper, a simple network model that is essential in orde... View full abstract»

• ### Stability Analysis of a Class of Nonlinear Fractional-Order Systems

Publication Year: 2008, Page(s):1178 - 1182
Cited by:  Papers (73)
| | PDF (371 KB) | HTML

In this paper, a stability theorem of nonlinear fractional-order differential equations is proven theoretically by using the Gronwall-Bellman lemma. According to this theorem, the linear state feedback controller is introduced for stabilizing a class of nonlinear fractional-order systems. And, a new criterion is derived for designing the controller gains for stabilization, in which control paramet... View full abstract»

• ### Cryptanalysis of Chaotic Masking Secure Communication Systems Using an Adaptive Observer

Publication Year: 2008, Page(s):1183 - 1187
Cited by:  Papers (5)
| | PDF (678 KB) | HTML

This paper carries out a further cryptanalysis of two Lorenz-based masking secure communication systems, which have been recently attacked by a high-pass filter. As demonstrated with our simulations, high-pass filter attack works well only when the covered information signal is monotonic. However, with an adaptive observer, it is still possible to coarsely obtain the information signal and correct... View full abstract»

• ### Stability Criteria With Less LMI Variables for Neural Networks With Time-Varying Delay

Publication Year: 2008, Page(s):1188 - 1192
Cited by:  Papers (17)
| | PDF (148 KB) | HTML

In this letter, simplified delay-dependent stability criteria for neural networks are derived by using a simple integral inequality. The results are in terms of linear matrix inequalities (LMIs) and turn out to be equivalent to some existing results but include less number of LMI variables. This implies that some redundant variables in the existing stability criteria can be removed while maintaini... View full abstract»

• ### Embedding Compression in Chaos-Based Cryptography

Publication Year: 2008, Page(s):1193 - 1197
Cited by:  Papers (30)
| | PDF (202 KB) | HTML

An algorithm for embedding compression in the Baptista-type chaotic cryptosystem is proposed. The lookup table used for encryption is determined adaptively by the probability of occurrence of plaintext symbols. As a result, more probable symbols will have a higher chance to be visited by the chaotic search trajectory. The required number of iterations is small and can be represented by a short cod... View full abstract»

• ### A Note on “Global Robust Stability Criteria for Interval Delayed Neural Networks Via an LMI Approach”

Publication Year: 2008, Page(s):1198 - 1202
Cited by:  Papers (5)
| | PDF (156 KB) | HTML

A recently reported result concerning the global exponential robust stability of delayed neural networks is revisited. It is shown by a counter example that the result is invalid because the proof is incorrect, and then a modified version is given. The paper also presents an improved sufficient condition for global exponential robust stability of the neural networks with unbounded activation funct... View full abstract»

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org