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Design & Test of Computers, IEEE

Issue 6 • Date Nov.-Dec. 2008

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Displaying Results 1 - 23 of 23
  • [Front cover]

    Publication Year: 2008 , Page(s): c1
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  • [Advertisement]

    Publication Year: 2008 , Page(s): c2
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  • Special Issue on 3D IC Design and Test

    Publication Year: 2008 , Page(s): 505
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  • [Table of contents]

    Publication Year: 2008 , Page(s): 506
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  • Design and test for reliability and efficiency

    Publication Year: 2008 , Page(s): 508
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    First Page of the Article
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  • Staff listing

    Publication Year: 2008 , Page(s): 509
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  • The State of ESL Design [Roundtable]

    Publication Year: 2008 , Page(s): 510 - 519
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB) |  | HTML iconHTML  

    This is the first of two roundtables on electronic system-level design in this issue of IEEE Design & Test. ESL design and tools have been present in the design landscape for many years. Significant ESL innovations are now part of most advanced design methodologies, spanning the domains of modeling, simulation, and synthesis. Techniques such as transaction-level modeling, automatic interconnection generation, behavioral synthesis, automatic instruction-set customization, retargetable compilers, and many others are currently used in the design of multimillion-gate chips. Yet, ESL design still seems to struggle to live up to the promise of providing increased productivity and design quality. This roundtable examines these issues and attempts to provide a definite picture of where ESL design is today and where it might be in the next five to 10 years. The participants in this roundtable include well-known experts in ESL design from the user side, universities, and tool providers. IEEE Design & Test thanks the roundtable participants: moderator Reinaldo Bergamaschi (CadComponents), Luca Benini (University of Bologna), Krisztian Flautner (ARM UK), Wido Kruijtzer (NXP Semiconductors), Alberto Sangiovanni-Vincentelli (University of California, Berkeley), and Kazutoshi Wakabayashi (NEC Japan). D&T gratefully acknowledges the help of Roundtables Editor Bill Joyner (Semiconductor Research Corp.), who organized the event. View full abstract»

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  • Advances in ESL Design

    Publication Year: 2008 , Page(s): 520 - 526
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    This is the second of two roundtables on electronic system-level (ESL) design, which recently has been seen as an advance in the EDA community--the latest attempt to improve designer productivity, shorten design time and cost, and improve design quality. Of course, "ESL" means different things to different people, and the notion varies even geographically--for example, between the US and Europe. The goal of this roundtable is to identify expectations and any meaningful advances associated with the notion of ESL design. What are the promising developments in the area? Which problems are relevant, and which are not? IEEE Design & Test thanks the roundtable participants: moderator Rajesh Gupta (University of California, San Diego), Arvind (Massachusetts Institute of Technology), Gerard Berry (Esterel Technologies), and Forrest Brewer (University of California, Santa Barbara). D&T gratefully acknowledges the help of Roundtables Editor Bill Joyner (Semiconductor Research Corp.), who organized the event. View full abstract»

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  • Wafer Test Methods to Improve Semiconductor Die Reliability

    Publication Year: 2008 , Page(s): 528 - 537
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (706 KB) |  | HTML iconHTML  

    Incremental advances in semiconductor device testing have improved device quality and reliability. New test methods applied to dies at the wafer level are now significantly improving the reliability of devices sold to the increasing bare-die market and reducing burn-in requirements for packaged devices. View full abstract»

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  • Building an FoC Using Large, Buffered Crossbar Cores

    Publication Year: 2008 , Page(s): 538 - 548
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (847 KB) |  | HTML iconHTML  

    The latest improvements in CMOS technologies have eliminated buffered crossbar memory requirements. Combined with a novel microarchitecture approach, these new technologies allow for implementation of a combined input-crosspoint queuing (CICQ), single-chip 32 times 32 switch as the core for a future fabric on a chip (FoC). This switch operates directly on variable-size packets, reducing overall data path complexity and increasing effective bandwidth. View full abstract»

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  • Defect Tolerance for Nanoscale Crossbar-Based Devices

    Publication Year: 2008 , Page(s): 549 - 559
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    The need for defect maps and per-chip placement and routing limits the efficiency of test and defect tolerance techniques in nanoscale crossbar-based devices. The authors propose a method using two simulation programs that circumvents these difficulties to find fault-free implementations of logic functions on defective crossbars. View full abstract»

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  • A Systematic Approach to Memory Test Time Reduction

    Publication Year: 2008 , Page(s): 560 - 570
    Cited by:  Papers (1)
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    This article describes a method for reducing overall memory test time without sacrificing fault coverage. Key to this method is a test time reduction tool that helps remove redundant test items from the test flow, merge existing test patterns, and develop efficient new test patterns. View full abstract»

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  • Advertiser/Product Index

    Publication Year: 2008 , Page(s): 571
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  • Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

    Publication Year: 2008 , Page(s): 572 - 580
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (663 KB) |  | HTML iconHTML  

    Networks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs. NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area. This article describes two approaches to implementing a distributed NoC in a GALS environment. View full abstract»

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  • Application Scenarios in Streaming-Oriented Embedded-System Design

    Publication Year: 2008 , Page(s): 581 - 589
    Cited by:  Papers (8)
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    A design method for handling increasingly dynamic real-time embedded-system applications can help developers cope with stringent system and market requirements. This method groups an application's operation modes into application scenarios and describes how to incorporate them in the overall design process. An automated scenario-based design trajectory reduces the energy consumption of a streaming application running on a single processor platform via dynamic voltage and frequency scaling. View full abstract»

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  • Managing Security in FPGA-Based Embedded Systems

    Publication Year: 2008 , Page(s): 590 - 598
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB) |  | HTML iconHTML  

    FPGAs combine the programmability of processors with the performance of custom hardware. As they become more common in critical embedded systems, new techniques are necessary to manage security in FPGA designs. This article discusses FPGA security problems and current research on reconfigurable devices and security, and presents security primitives and a component architecture for building highly secure systems on FPGAs. View full abstract»

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  • Design Automation Technical Committee Newsletter

    Publication Year: 2008 , Page(s): 599
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  • The two faces of high-level synthesis [review of High-Level Synthesis: From Algorithm to Digital Circuit (Coussy, P. and Morawiec, A., Eds., 2008)]

    Publication Year: 2008 , Page(s): 600 - 601
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    Reviewed in this issue is High-Level Synthesis: From Algorithm to Digital Circuit, edited by Philippe Coussy and Adam Morawiec (Springer, 2008, ISBN: 978-1-4020-8587-1, 300 pp., $129). View full abstract»

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  • Test Technology TC Newsletter

    Publication Year: 2008 , Page(s): 602 - 603
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  • CEDA Currents

    Publication Year: 2008 , Page(s): 604 - 606
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  • Clarifying the record on testability cost functions

    Publication Year: 2008 , Page(s): 608 - 609
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    Many articles have been written on testability cost functions and measures. Most of them point to the work of Lawrence Goldstein as one of the first major contributions in this field.4 In this column, the author describes his personal familiarity with some of this early work in an effort to clarify the genesis of these ideas. View full abstract»

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  • [Advertisement]

    Publication Year: 2008 , Page(s): c3
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  • [Advertisement]

    Publication Year: 2008 , Page(s): c4
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty