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Device and Materials Reliability, IEEE Transactions on

Issue 4 • Date Dec. 2008

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Displaying Results 1 - 18 of 18
  • [Front cover]

    Publication Year: 2008 , Page(s): C1
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  • IEEE Transactions on Device and Materials Reliability publication information

    Publication Year: 2008 , Page(s): C2
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  • Table of contents

    Publication Year: 2008 , Page(s): 633
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  • Kudos to Our Reviewers

    Publication Year: 2008 , Page(s): 634
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  • Time-Dependent Dielectric Breakdown of 4H-SiC/  \hbox {SiO}_{2} MOS Capacitors

    Publication Year: 2008 , Page(s): 635 - 641
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (311 KB) |  | HTML iconHTML  

    Time-dependent dielectric breakdown (TDDB) is one of the major issues concerning long-range reliability of dielectric layers in SiC-based high-power devices. Despite the extensive research on TDDB of SiO2 layers on Si, there is a lack of high-quality statistical TDDB data of SiO2 layers on SiC. This paper presents comprehensive TDDB data of 4H-SiC capacitors with a SiO2 gate insulator collected over a wide range of electric fields and temperatures. The results show that at low fields, the electric field acceleration parameter is between 2.07 and 3.22 cm/MV. At fields higher than 8.5 MV/cm, the electric field acceleration parameter is about 4.6 cm/MV, indicating a different failure mechanism under high electric field stress. Thus, lifetime extrapolation must be based on failure data collected below 8.5 MV/cm. Temperature acceleration follows the Arrhenius model with activation energy of about 1 eV, similar to thick SiO2 layers on Si. Based on these experimental data, we propose an accurate model for lifetime assessment of 4H-SiC MOS devices considering electric field and temperature acceleration, area, and failure rate percentile scaling. It is also demonstrated that temperatures as high as 365degC can be used to accelerate TDDB of SiC devices at the wafer level. View full abstract»

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  • Dielectric Charging in Electrostatically Actuated MEMS Ohmic Switches

    Publication Year: 2008 , Page(s): 642 - 646
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB) |  | HTML iconHTML  

    MEMS switches having separate signal and actuation electrodes with different air gaps are fabricated using a copper-based CMOS interconnect manufacturing process. By using a control voltage high enough to establish metal-metal contact between the signal electrodes while avoiding contact between the dielectric-covered actuation electrodes, dielectric charging appears to be tolerable. By simultaneously measuring the conductance across the signal electrodes and the capacitance across the actuation electrodes, the conductance-force characteristic can be readily monitored and analyzed. For the present switches, the effect of polarization charge appears to be negligible, and dielectric charging is significant only after dielectric contact is made and space charge is injected. View full abstract»

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  • The Effect of Electrode Layout on Nitride-Based Light-Emitting Diodes

    Publication Year: 2008 , Page(s): 647 - 651
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (302 KB) |  | HTML iconHTML  

    Nitride-based light-emitting diodes (LEDs) with different electrode layouts were fabricated and analyzed. The turn-on voltage (V f) was proved to be highly related to the layout design of N-extending electrode. In addition, the electroluminescence intensity was almost proportional to the area of transparent contact layer (A TCL) subtracting the area of P-extending electrode (A P). Moreover, the current spreading was highly sensitive to the location and route of P- and N-extending electrodes. Good location and route can avoid thermal effect and damage. Finally, this paper proposed an easy and direct concept to estimate and predict the performance of nitride-based LEDs in turn-on voltage, electroluminescence intensity, and current spreading. It was highly potential to improve and change the currently mask design of nitride-based LEDs. View full abstract»

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  • The Analysis of System-Level Timing Failures Due to Interconnect Reliability Degradation

    Publication Year: 2008 , Page(s): 652 - 663
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (968 KB) |  | HTML iconHTML  

    The continuous scaling of feature dimensions and the introduction of new dielectric materials are pushing interconnects closer to their reliability limits. Degradation mechanisms are becoming more pronounced, making the interconnect lifetime a challenge at the level of process qualification. Moreover, these mechanisms exhibit new properties, such as gradual degradation of electrical parameters instead of abrupt breakdown phenomena. As a result, it becomes more likely that systems will fail because one of their transistors or wires becomes gradually too slow. These soft failures are not captured by existing tools. The methodology introduced in this paper estimates the impact of two dominant interconnect degradation mechanisms (electromigration and time-dependent dielectric breakdown) on the total system performance. This constitutes a first step toward system-level-driven reliability-aware design for interconnects. View full abstract»

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  • Reliability Assessment of Micromachined Fixed–Fixed Beam Based on FE Simulation and Probabilistic Sampling

    Publication Year: 2008 , Page(s): 664 - 670
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1167 KB) |  | HTML iconHTML  

    Recent trends in structural mechanics applications of finite-element methods (FEM) show an increasing demand for efficient analysis tools. This paper presents a realistic approach for modeling a fixed-fixed beam structure used in microelectromechanical systems based on finite-element analysis (FEA). The use of probabilistic methods to assess the electromechanical behavior of the beam under the presence of micromachine manufacturing and process uncertainties is also presented. The finite-element model of the beam is constructed using the commercial code ANSYS (10.0). In the standard approach of modeling, existing literature assumes deterministic values for design parameters. However, fabrication of the device introduces some amount of variation in these parameters. In this paper, the probabilistic approach is discussed to account for the variability in fabrication. FEA guides the design of fixed-fixed beam to achieve a robust and reliable design in a most efficient way. From the probabilistic analysis, it was observed that the changes in length and thickness tend to be the most influencing parameters, which need to be tightly controlled. View full abstract»

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  • Power-Substrate Static Thermal Characterization Based on a Test Chip

    Publication Year: 2008 , Page(s): 671 - 679
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (931 KB) |  | HTML iconHTML  

    Thermal simulation is, nowadays, a basic tool to predict temperature distributions and heat fluxes of complex packages and modules. These variables are of main importance in high-power assemblies to analyze and predict their reliability limits. Nevertheless, the simulation results can be inaccurate due to the uncertainty of the values of the physical parameters involved in the models, as it is the case for the thermal conductivity of the dielectric layers (ceramics and composites) of the main families of power substrates [direct copper bonded (DCB) and insulated metal substrate (IMS)]. We propose a methodology for the in situ determination of these thermal conductivities under true operation conditions. Three test assemblies based on a thermal test chip and different types of power substrates (two IMS and one DCB) have been characterized in order to deduce their thermal resistance. Three-dimensional numerical models of the assemblies have also been developed. Thereby, the thermal conductivity of the critical layers is derived by minimizing the error between the experimental and the simulated thermal resistances. From the subsequent simulation results, the vertical temperature distributions are analyzed in order to predict the thermal stresses of the different layers inside the substrates. View full abstract»

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  • Electromigration-Induced Failure Characteristics of Spin-Valve Multilayers for Metallic-Based Spintronic Devices

    Publication Year: 2008 , Page(s): 680 - 688
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (534 KB) |  | HTML iconHTML  

    Electromigration (EM) failure characteristics of patterned NiFe/Cu/NiFe spin-valve (SV) multilayers (MLs) with or without thin Co diffusion barrier inserted at the interface between NiFe and Cu layers have been investigated by applying a constant dc current with different current densities to predict the electrical and magnetic stabilities of metallic SV-based spintronic devices. It was experimentally verified that the Ni-Cu intermixing caused by the EM-induced Cu interdiffusion to the top or bottom NiFe layer plays a dominant role in determining the EM-induced failure characteristics of the NiFe/(Co)/Cu/(Co)/NiFe SV multilayered devices. In addition, it was clearly demonstrated that the interlayer (indirect) exchange coupling field and the magnetic moment of the NiFe/(Co)/Cu/(Co)/NiFe SV-MLs are strongly dependent on the EM-failure induced Ni-Cu intermixing directly relevant to the Cu spacer interdiffusion. The failure mechanism of NiFe/(Co)/Cu/(Co)/NiFe SV multilayered devices showed ldquobimodal failure characteristics.rdquo The critical current density (Jc) for such a bimodal failure mechanism was found to be determined at Jc = 7 times107A/cm2 When J les Jc, the failure was mainly caused by the electrostatic force (or electron wind force) accelerating an interdiffusion through grain boundaries that leads to forming typical EM failures such as voids and hillocks. Whereas, when J > Jc, a melting or a vaporization dominantly accelerated by the Joule heating played more significant role and caused the catastrophic failures. The NiFe/Co/Cu/Co/NiFe SV-MLs showed a much longer mean time-to-failure (t50) than that of NiFe/Cu/NiFe SV-MLs. This experimental result implies that an ultrathin Co insertion layer is effective to improve the EM-induced failure lifetime due to its restraining effects as a diffusion barrier to prevent Cu interdiffusion to both the top and bottom NiFe layers. Furtherm- - ore, this result directly verified that Ni-Cu intermixing is the dominant factor in determining the EM characteristics of the NiFe/Cu/NiFe SV multilayered spintronic devices. View full abstract»

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  • Temperature Effects on Breakdown Characteristics of High- \kappa Gate Dielectrics With Metal Gates

    Publication Year: 2008 , Page(s): 689 - 693
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (719 KB) |  | HTML iconHTML  

    In this paper, the temperature dependence of time-dependent dielectric breakdown (BD) and stress-induced leakage current (SILC) of high-kappa and interfacial layers (ILs) are studied separately and in a gate stack with metal gates as the BD mechanisms of these layers are different at higher temperatures than at room temperature. As observed from the low voltage SILC, the IL initiates the gate stack BD process at elevated temperature, which is followed by the high-kappa layer. Activation energy extracted from Weibulll distribution of time-to-BD (T BD) data from high-kappa layer further suggests that the gate stack BD occurs when high- kappa layer ultimately breaks down. View full abstract»

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  • Investigation on Board-Level CDM ESD Issue in IC Products

    Publication Year: 2008 , Page(s): 694 - 704
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1563 KB) |  | HTML iconHTML  

    The impacts caused by board-level charged-device-model (CDM) electrostatic-discharge (ESD) events on integrated-circuit products are investigated in this paper. The mechanism of board-level CDM ESD event is introduced first. Based on this mechanism, an experiment is performed to investigate the board-level CDM ESD current waveforms under different sizes of printed circuit boards (PCBs), charged voltages, and series resistances in the discharging path. Experimental results show that the discharging current strongly depends on the PCB size, charged voltage, and series resistance. Moreover, the chip- and board-level CDM ESD levels of several test devices and test circuits fabricated in CMOS processes are characterized and compared. The test results show that the board-level CDM ESD level of the test circuit is lower than the chip-level CDM ESD level of the test circuit, which demonstrates that the board-level CDM ESD event is more critical than the chip-level CDM ESD event. In addition, failure analysis reveals that the failure in the test circuit under board-level CDM ESD test is much severer than that under chip-level CDM ESD test. View full abstract»

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  • Temperature Stability Analysis of CMOS-SAW Devices by Embedded Heater Design

    Publication Year: 2008 , Page(s): 705 - 713
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1360 KB) |  | HTML iconHTML  

    The design, finite element (FE) modeling, and electrical characterization of an embedded heater in complementary metal-oxide-semiconductor (CMOS) are presented. The heater is used to analyze the temperature stability behavior of CMOS-surface acoustic wave (SAW) devices. The heater employs n-well layer of standard CMOS technology to provide high efficiency resistive heating without physically perturbing the SAW architectures and performances. A detailed 3-D model and FE investigation is laid out to characterize the heat, current, temperature, and thermal energy distributions within the substrate and the piezoelectric material of interest ZnO. Electrical characterization based on Wheatstone configuration is presented to analyze the temperature stability of the sputtered ZnO and the CMOS-SAW delay lines. A temperature coefficient of frequency of -48.815/degC for the fabricated SAW devices with operating frequency of 322.5 MHz is obtained. The experimental results show close agreement with the FE simulations. The results demonstrate that the embedded heater design can be used as a robust analytical tool to investigate temperature stability of CMOS-SAW devices and potentially be utilized as an on-chip element for chemical, biological, and temperature sensor applications. View full abstract»

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  • Special issue of IEEE Transactions on Electron Devices

    Publication Year: 2008 , Page(s): 714
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  • 2008 Index IEEE Transactions on Device and Materials Reliability Vol. 8

    Publication Year: 2008 , Page(s): 715 - 728
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  • IEEE Transactions on Device and Materials Reliability information for authors

    Publication Year: 2008 , Page(s): C3
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  • Blank page [back cover]

    Publication Year: 2008 , Page(s): C4
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Aims & Scope

IEEE Transactions on Device and Materials Reliability is published quarterly. It provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the manufacture of these devices; and the interfaces and surfaces of these materials.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Anthony S. Oates
Taiwan Semiconductor Mfg Co.