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# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 25 of 27

Publication Year: 2008, Page(s):C1 - C4
| PDF (43 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2008, Page(s): C2
| PDF (39 KB)
• ### Analysis and Design of a Wide-Tuning-Range VCO With Quadrature Outputs

Publication Year: 2008, Page(s):1209 - 1213
Cited by:  Papers (21)
| | PDF (656 KB) | HTML

A quadrature voltage-controlled oscillator (QVCO) with a wide tuning range is proposed and implemented in the TSMC 0.18- mum CMOS process. The said QVCO uses a cross-coupled structure and a current-reuse technology to produce the quadrature signal and to save power consumption and area, respectively. Based on our measurement, the phase noise with 1-MHz offset from the carrier frequency of 3.6 GHz ... View full abstract»

• ### Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs

Publication Year: 2008, Page(s):1214 - 1218
Cited by:  Papers (14)
| | PDF (786 KB) | HTML

Full-rate bang-bang phase detectors (BBPDs) and bang-bang frequency detectors (FDs) are presented for continuous-rate clock and data recovery (CDR) circuits. The proposed BBPDs have only six latches, so they save the power and area. Their symmetric architecture minimizes the clock skew caused by the nonsymmetric layout. The proposed unilateral FDs have a wide detectable frequency range. The theore... View full abstract»

• ### Capacitor-Swapping Cyclic A/D Conversion Techniques With Reduced Mismatch Sensitivity

Publication Year: 2008, Page(s):1219 - 1223
Cited by:  Papers (6)  |  Patents (1)
| | PDF (213 KB) | HTML

This work proposes two capacitor-swapping techniques, random feedback-capacitor interchanging (RFCI) and averaging RFCI (ARFCI) techniques, for cyclic analog-to-digital converters (ADCs) to reduce the harmonic distortion caused by capacitor mismatch without trimming or calibration. The proposed RFCI and ARFCI techniques can be realized by simply rearranging the capacitor connections of the ADCs in... View full abstract»

• ### Combining Multipath and Single-Path Time-Interleaved Delta-Sigma Modulators

Publication Year: 2008, Page(s):1224 - 1228
Cited by:  Papers (5)
| | PDF (232 KB) | HTML

In this brief, single-path time-interleaved delta-sigma modulators are analyzed and evaluated. It is found that finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the architecture. A hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of... View full abstract»

• ### Low Voltage Differential Input Stage With Improved CMRR and True Rail-to-Rail Common Mode Input Range

Publication Year: 2008, Page(s):1229 - 1233
Cited by:  Papers (6)
| | PDF (900 KB) | HTML

A scheme for low voltage rail-to-rail operation with improved common mode rejection ratio is introduced. It can operate with single supply voltages close to a transistor's threshold voltage and it is very compact and power efficient. It is based on a differential amplifier with floating gate input transistors featuring dynamical adjustment of a floating gate biasing voltage. This reduces significa... View full abstract»

• ### An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design

Publication Year: 2008, Page(s):1234 - 1238
Cited by:  Papers (26)  |  Patents (2)
| | PDF (465 KB) | HTML

In this paper, an efficient VLSI architecture of a pipeline fast Fourier transform (FFT) processor capable of producing the normal output order sequence is presented. A new FFT design based on the decimated dual-path delay feed-forward data commutator unit by splitting the input stream into two half-word streams is first proposed. The resulting architecture can achieve full hardware efficiency suc... View full abstract»

• ### Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator

Publication Year: 2008, Page(s):1239 - 1243
Cited by:  Papers (14)
| | PDF (243 KB) | HTML

This paper presents a new efficient architecture for the design of fast low-cost single-clock-cycle binary comparators. The proposed 64-bit circuit requires only 1051 transistors and, when implemented by using the ST 90-nm 1-V CMOS technology, it exhibits a running frequency higher than 4 GHz with an average power dissipation of only ~ 4 mW. Comparison with the fastest comparator known in the lite... View full abstract»

• ### A Systolic Array 2-D IIR Broadband RF Beamformer

Publication Year: 2008, Page(s):1244 - 1248
Cited by:  Papers (20)
| | PDF (824 KB) | HTML

A systolic architecture is proposed for the real-time implementation of broadband 2-D IIR beam filters having applications in ultra-wideband (UWB) radio frequency (RF) antenna arrays. Real-time throughputs of one-frame-per-clock-cycle are achieved. A finite-difference time-domain computational electromagnetic model of a typical indoor propagation environment is used to illustrate that the method s... View full abstract»

• ### Low-Cost Hardware-Sharing Architecture of Fast 1-D Inverse Transforms for H.264/AVC and AVS Applications

Publication Year: 2008, Page(s):1249 - 1253
Cited by:  Papers (15)  |  Patents (1)
| | PDF (237 KB) | HTML

In this paper, the fast one-dimensional (1-D) algorithms and their hardware-sharing designs for the 1-D 2times2, 4times4, and 8times8 inverse transforms of H.264/AVC and the 1-D 8times8 inverse transform of AVS are proposed with the low hardware cost, especially for the multiple decoding applications in China. By sharing the hardware, the proposed 1-D hardware sharing architecture is realized by a... View full abstract»

• ### Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders

Publication Year: 2008, Page(s):1254 - 1258
Cited by:  Papers (7)  |  Patents (1)
| | PDF (665 KB) | HTML

By optimizing the number of look-ahead steps of the first layer of the previous low-latency architectures for M-step look-ahead high-throughput rate Viterbi decoders, this paper improves the hardware efficiency by large percentage with slight increase or even further decrease of the latency for the add-compare-select (ACS) computation. This is true especially when the encoder constraint length (K)... View full abstract»

• ### A Robust ICA-Based Adaptive Filter Algorithm for System Identification

Publication Year: 2008, Page(s):1259 - 1263
Cited by:  Papers (10)
| | PDF (178 KB) | HTML

This paper proposes a new adaptive filter algorithm for system identification using independent component analysis. The additive noise is considered as an independent component to be separated from the noisy observation and is simultaneously estimated online. The proposed algorithm is derived by minimizing the mutual information between the estimated additive noise and the input signal. The local ... View full abstract»

• ### Design of Exactly Linear Phase $K$-Regular IIR Half-Band Filter

Publication Year: 2008, Page(s):1264 - 1268
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This paper proposes a novel method to design exactly linear phase infinite impulse response half-band filters with arbitrary regularity. Broadly speaking, the design problem is formulated as a semi-infinite program, which is then turned into a semidefinite program of minimal order via a new linear matrix inequality characterization of convex hulls of trigonometric polynomials. In contrast to maxim... View full abstract»

• ### Analysis of Zero-Order Holder Discretization of Two-Dimensional Sliding-Mode Control Systems

Publication Year: 2008, Page(s):1269 - 1273
Cited by:  Papers (28)
| | PDF (226 KB) | HTML

This paper presents a study of discretization behaviors of two-dimensional equivalent control-based sliding mode control systems. Steady-state behaviors are classified and their bounds are found. Conditions under which the system trajectory in the steady state spends at most two iterations on each side of the sliding surface are given. Theoretical results are illustrated with simulation examples. View full abstract»

• ### Synchronization in Networks of Hindmarsh–Rose Neurons

Publication Year: 2008, Page(s):1274 - 1278
Cited by:  Papers (13)
| | PDF (276 KB) | HTML

Synchronization is deemed to play an important role in information processing in many neuronal systems. In this work, using a well known technique due to Pecora and Carroll, we investigate the existence of a synchronous state and the bifurcation diagram of a network of synaptically coupled neurons described by the Hindmarsh-Rose model. Through the analysis of the bifurcation diagram, the different... View full abstract»

• ### Fault Tolerance Analysis for Switched Systems Via Global Passivity

Publication Year: 2008, Page(s):1279 - 1283
Cited by:  Papers (32)
| | PDF (254 KB) | HTML

In this brief, we introduce the passivity theory into the fault tolerance analysis for switched systems. We propose a ldquoglobal passivityrdquo concept which means that the total energy stored by the switched system is less than the total energy supplied from the outside. The individual passivity of each mode is not required, and the stability of the system can be achi... View full abstract»

• ### Stabilizing Effects of Impulses in Delayed BAM Neural Networks

Publication Year: 2008, Page(s):1284 - 1288
Cited by:  Papers (21)
| | PDF (169 KB) | HTML

This brief studies the stabilizing effects of impulses in delayed bidirectional associative memory (DBAM) neural networks when its continuous component does not converge asymptotically to the equilibrium point. A general criterion, which characterizes the aggregated effects of the impulse and the deviation of its continuous component from the equilibrium point on the exponential stability of the c... View full abstract»

• ### Rejection of Nonharmonic Disturbances in Nonlinear Systems With Semi-Global Stability

Publication Year: 2008, Page(s):1289 - 1293
Cited by:  Papers (12)
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An asymptotic rejection algorithm is proposed for nonlinear dynamic systems under nonharmonic periodic disturbances generated from nonlinear exosystems. The dynamic systems considered in this brief are in the normal form, a larger class of nonlinear dynamic systems than the output feedback systems. A new internal model design method is used to exploit the nonlinearities in the exosystem, together ... View full abstract»

• ### Robust $D$ -Stability for a Class of Complex Singularly Perturbed Systems

Publication Year: 2008, Page(s):1294 - 1298
Cited by:  Papers (4)
| | PDF (153 KB) | HTML

This brief is concerned with the robust D-stability problem for a class of complex singularly perturbed systems with state delay. According to singular system approach, sufficient conditions, which are tested easily, are obtained by introduce delay-dependent state feedback, to ensure that the two-time-scale systems are regular, impulse free and D -stable, that is, all its poles are l... View full abstract»

• ### Tightness Conditions for Semidefinite Relaxations of Forms Minimization

Publication Year: 2008, Page(s):1299 - 1303
Cited by:  Papers (5)
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The Gram matrix allows to compute a lower bound of the minimum of a form via an LMI (linear matrix inequality) optimization by exploiting SOS (sum of squares) relaxations. This paper introduces and characterizes the Gram-tight forms, i.e. forms whose minimum coincides with this lower bound. In particular, it is shown that one can establish that a form is Gram-tight just by checking whether the dim... View full abstract»

• ### Unified Structure of Basic UWB Waveforms

Publication Year: 2008, Page(s):1304 - 1308
Cited by:  Papers (2)
| | PDF (358 KB) | HTML

In this brief, a generalized expression for the popular ultra wideband waveforms is derived. It is shown that all three waveforms used in ultra wideband (Gaussian, modified Hermite, and prolate spheroidal waveforms) fulfill the Sturm-Liouville differential equation. By using this unified structure, characteristics of the waveforms such as orthogonality, finite duration in time and frequency spectr... View full abstract»

• ### Reduced Complexity Algorithm for Spreading Sequence Design

Publication Year: 2008, Page(s):1309 - 1313
Cited by:  Papers (1)
| | PDF (251 KB) | HTML

This paper describes a novel gradient descent algorithm for the constrained optimization of spreading sequence design in the uplink of CDMA systems that use codeword adaptation. We prove that the proposed algorithm converges to the optimal sequence. In addition, the paper demonstrates the convergence of the parallel distributed optimization which is confirmed by simulations. Parallel optimization ... View full abstract»

• ### Corrections to "Chaos-Coded Modulation Over Rician and Rayleigh Flat Fading Channels"

Publication Year: 2008, Page(s): 1314
| | PDF (23 KB) | HTML

First Page of the Article
View full abstract»

• ### 2008 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 55

Publication Year: 2008, Page(s):1315 - 1346
| PDF (398 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org