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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 11 • Date Dec. 2008

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Displaying Results 1 - 25 of 44
  • Table of contents

    Page(s): C1
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): C2
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    Freely Available from IEEE
  • Feedforward-Regulated Cascode OTA for Gigahertz Applications

    Page(s): 3373 - 3382
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1193 KB) |  | HTML iconHTML  

    A very high-frequency operational transconductance amplifier (OTA) with a new feedforward-regulated cascode topology is demonstrated in this paper. Experimental results show a bandwidth of 10 GHz and a large transconductance of 11 mS. A theoretical analysis of the OTA is provided which is in very good agreement with the measured results. We also carry out a Monte Carlo simulation to determine the effect of transistor mismatches and process variations on the transconductance and input/output parasitic capacitances of the OTA. The linearity and intermodulation distortion properties of the OTA, which are of particular interest in microwave applications, are experimentally determined using a purpose-built single-stage amplifier. For high-frequency demonstration purposes we built a larger circuit: an inductor less microwave oscillator. The fabricated oscillator operates at 2.89 GHz and has a significantly larger output voltage swing and better power efficiency than other inductor less oscillators reported in the literature in this frequency range. It also has a very good phase noise for this type of oscillators: -116 dBc/Hz at 1-MHz offset. View full abstract»

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  • Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion

    Page(s): 3383 - 3392
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (753 KB) |  | HTML iconHTML  

    Dynamic element matching (DEM) is widely used in multibit digital-analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performance-enabling technique in delta-sigma data converters which require low-resolution but high-linearity DACs. More recently, segmented DEM architectures have made high-resolution Nyquist-rate DEM DACs practical. However, the previously published segmented DEM DAC designs have been ad hoc. Systematic techniques for synthesizing segmented DEM DACs and analyses of their design tradeoffs have not been published previously. This paper quantifies a fundamental power dissipation versus complexity tradeoff implied by segmentation and provides a systematic method of synthesizing segmented DEM DACs that are optimal in terms of the tradeoff. View full abstract»

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  • IIR Filter Adaptation Using Branch-and-Bound: A Novel Approach

    Page(s): 3393 - 3403
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (626 KB) |  | HTML iconHTML  

    Adaptive infinite impulse response (IIR) filters provide significant advantages over equivalent finite impulse response (FIR) implementations because they are able to more accurately model physical plants that have pole-zero structures. Additionally, they are typically capable of meeting performance specifications using fewer filter parameters. This savings in parameters, which can be as much as 5-10 times, leads to the use of fewer multiplier blocks and therefore, lower power consumption. Despite these advantages, adaptive IIR filters have not found widespread use because the associated mean squared error (MSE) cost function is multimodal and therefore, significantly difficult to minimize. Additionally, the filter can become unstable during adaptation. These two properties pose several problems for adaptive algorithms, causing them to be sensitive to initial conditions, produce biased solutions, unstable filter configurations or converge to local minima. These problems prevent the widespread use of adaptive IIR filters in practice and if such filter structures are to become more practical, new, innovative solutions are required. This paper proposes a new algorithm for minimizing the MSE cost function of adaptive IIR filters aimed at addressing some of the aforementioned issues. We adopt the approach of using a branch-and-bound algorithm, which is an exhaustive search method, and employ interval arithmetic for all computations. Simulation results show that the resulting algorithm is viable and competitive and, when compared with a number of existing state-of-the-art algorithms, outperforms them in terms of the MSE of the final point. View full abstract»

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  • Low-Voltage Log-Domain Complex Filters

    Page(s): 3404 - 3412
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB) |  | HTML iconHTML  

    Two systematic methods for designing low-voltage log-domain complex filters are introduced in this paper. The first one is based on the transposition of the signal flow graph representation of the linear-domain complex leapfrog prototype filter to the corresponding one in the log-domain. The last one is based on the transposition of the wave equivalents of the elements of the complex passive prototype filter to the corresponding log-domain complex equivalents. Both transpositions are performed by employing an appropriate set of complementary operators that facilitates the derivation of low-voltage log-domain filter configurations. Two design examples are given, where a 12th-order log-domain complex transfer function is realized in order to fulfill the Bluetooth specifications. The derived log-domain filter structures operate at a single 1.2-V-power supply-voltage, and their behavior was evaluated through simulation results. In addition, a comparison concerning important quality factors of both of the proposed structures is performed, and the obtained results are further discussed. View full abstract»

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  • Stability of Hybrid Stochastic Retarded Systems

    Page(s): 3413 - 3420
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (435 KB) |  | HTML iconHTML  

    In the past few years, hybrid stochastic retarded systems (also known as stochastic retarded systems with Markovian switching), including hybrid stochastic delay systems, have been intensively studied. Among the key results, Mao et al. proposed the Razumikhin-type theorem on exponential stability of stochastic functional differential equations with Markovian switching and its application to hybrid stochastic delay interval systems. However, the importance of general asymptotic stability has not been considered. This paper is to study Razumikhin-type theorems on general p-th moment asymptotic stability of hybrid stochastic retarded systems. The proposed theorems apply to complex systems including some cases when the existing results cannot be used. View full abstract»

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  • A Monte Carlo Particle Model Associated with Neural Networks for Tracking Problem

    Page(s): 3421 - 3429
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (570 KB) |  | HTML iconHTML  

    Sequential Monte Carlo (SMC) methods, namely, particle filters, are powerful simulation techniques for sampling sequentially from a complex probability distribution. SMC can be used to solve some problems associated with nonlinear non-Gaussian probability distribution. Sampling is a key step for these methods and has vital effects on simulation results. Various sampling strategies have been proposed to improve the simulation results of SMC methods, but degeneracy of particles sometimes is very severe so that there are only a few particles having significant weights. Diversity of particle samples is reduced significantly so that only a few particles are used to represent the corresponding probability distribution. This kind of sampling is not reasonable to approximate probability distribution. This paper addresses a new method which can avoid the phenomenon of particle degeneracy. We split particles with very big weights into two small ones and use the strategy of neural network to adjust positions of tail particles in order to increase their weights. Another advantage is that this method can efficiently make simulation results approach the actual object. Our simulation results of the typical tracking problem show that not only the phenomenon of particle degeneracy is effectively avoided but also tracking results are much better than those of the traditional particle filters. Compared with the move-resample method, our method shows better results under the same conditions. View full abstract»

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  • Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation

    Page(s): 3430 - 3437
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (758 KB) |  | HTML iconHTML  

    Given a set of numbers X, finding the minimum value of X, min_1st, is a very easy task. However, efficiently finding its second minimum value, min_2nd, requires the derivations of min_1st and finding the minimum value from the set of the remaining numbers. Efficient algorithms and cost-effective hardware of finding the two smallest of X are greatly needed for the low-density parity-check (LDPC) decoder design. The following two architectures are developed in this paper: (1) sorting-based (XS) approach and (2) tree structure (TS) approach. Experimental results show that the XS approach provides less number of comparisons, while the TS approach achieves higher speed performance at lower hardware cost. Since the hardware unit is repeatedly used in the LDPC decoder design, the proposed high-speed low-cost TS approach is strongly recommended. View full abstract»

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  • Conflict-Free Parallel Memory Accessing Techniques for FFT Architectures

    Page(s): 3438 - 3447
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (421 KB) |  | HTML iconHTML  

    Speeding up fast Fourier transform (FFT) computations is critical for today's real-time systems targeting signal processing and telecommunication applications. Aiming at the performance improvement and the efficiency of FFT architectures, this paper presents an address generation technique which enables a radix-b processor to access in parallel b memory banks without conflicts during each stage's computations. Using kb memory banks at each stage leads to increasing the speedup of the algorithm by a factor of kb . The address generation can be realized in each radix-b stage by the use of lookup tables of size O(kb 2) bits. The proposed technique is cost efficient and leads to the design of FFT architectures of high speedup and high sustained throughput. View full abstract»

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  • A Floating-Gate-Based Programmable CMOS Reference

    Page(s): 3448 - 3456
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1134 KB) |  | HTML iconHTML  

    We describe a compact programmable CMOS reference, where the reference is determined by the charge difference between two floating-gate transistors, thereby making the reference insensitive to temperature and other environmental effects. Using floating-gate transistors adds programmability making a wide range of reference voltages possible with negligible long-term drift. A prototype circuit has been implemented in a 0.35-mum CMOS process, and reference voltages ranging from 50 mV to 0.6 V have been achieved. We demonstrate a voltage reference programming accuracy of plusmn40 muV . Experimental results indicate a temperature sensitivity of approximately 53 muV/degC for a nominal reference voltage of 0.4 V over a temperature range of -60degC-140degC. View full abstract»

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  • A Polyphase Filter Design for Continuous-Time Quadrature Bandpass Sigma–Delta Modulators

    Page(s): 3457 - 3468
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (770 KB) |  | HTML iconHTML  

    This paper presents a strategy for successful polyphase-filter design for continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulators. Based on a low-pass filter with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is suited for implementation in low-power applications - analytical equations are derived. A new compensation scheme is proposed and implemented by cross-coupling additional resistors, without the necessity of extra-active components. Translation to intermediate frequency in second- and fourth-order polyphase filters with the proposed compensation scheme are compared to analytical considerations and simulation. Nonlinearities introduced by mismatch of feedforward coefficients and finite gain-bandwidth of amplifiers are considered. View full abstract»

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  • Closed-Form Orthogonal DFT Eigenvectors Generated by Complete Generalized Legendre Sequence

    Page(s): 3469 - 3479
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (972 KB) |  | HTML iconHTML  

    In this paper, we propose a new method for deriving the closed-form orthogonal discrete Fourier transform (DFT) eigenvectors of arbitrary length using the complete generalized Legendre sequence (CGLS). From the eigenvectors, we then develop a novel method for computing the DFT. By taking a specific eigendecomposition to the DFT matrix, after proper arrangement, we can derive a new fast DFT algorithm with systematic construction of an arbitrary length that reduces the number of multiplications needed as compared with the existing fast algorithm. Moreover, we can also use the proposed CGLS-like DFT eigenvectors to define a new type of the discrete fractional Fourier transform, which is efficient in implementation and effective for encryption and OFDM. View full abstract»

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  • A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators

    Page(s): 3480 - 3487
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1023 KB) |  | HTML iconHTML  

    Excess loop delay (ELD) is well known for its detrimental effect on the performance and stability of continuous-time sigma-delta modulators. A detailed analysis on the most recently published compensation techniques for single-stage modulators is performed in this paper, thus enabling their application to an arbitrary modulator. Based on different characteristics such as circuit complexity, achievable dynamic range, or requirements on the operational amplifiers, their advantages and disadvantages are investigated. Subsequently, the analysis is extended to cascaded modulators. Contrary to intuition, the results indicate that a compensation of ELD in every stage of the cascade is insufficient for optimal performance. Although not configured in a feedback configuration and as such not suffering from stability problems, each coupling network between two stages must additionally be compensated for ELD. View full abstract»

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  • On the Design of Undersampling Continuous-Time Bandpass Delta–Sigma Modulators for Gigahertz Frequency A/D Conversion

    Page(s): 3488 - 3499
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1200 KB) |  | HTML iconHTML  

    This paper describes issues and tradeoffs related to the design of undersampling delta-sigma modulators (DeltaSigmaMs) for wireless receivers. It proposes a new bandpass undersampling DeltaSigmaM architecture dedicated to multigigahertz frequencies. This paper is based on up-sampling in the feedback path to remove the analog mixer usually found in the modulator. Design equations are discussed for an optimum operating point when the input signal is at 1.8 GHz. The related design model can be applied to many communication standards. The underlying proposed architecture can receive high-frequency carriers modulated with signals of bandwidth as large as 5 MHz. In the proposed design, it converts the signal into digital data with a spurious-free dynamic range of 46 dB at a sampling frequency of 810.1 MHz. Design simulation, characterization, and implementation of the proposed modulator are done using a 0.13- mum CMOS technology. View full abstract»

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  • Color Superresolution Reconstruction and Demosaicing Using Elastic Net and Tight Frame

    Page(s): 3500 - 3512
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6653 KB) |  | HTML iconHTML  

    The goal of color superresolution reconstruction and demosaicing is to get an enhanced resolution image from raw single-chip data of Bayer color filter array. Two parts of regularization method, fidelity and regularization terms, are discussed in detail to solve the problem. Elastic net is successfully applied to variable-selection method; we utilize it as a novel fidelity term to improve performance and make the reconstructed image more suitable for human visual system. Piecewise linear framelet operators are recently adopted to image denoising, which are utilized to detect multiorientation variation of the signal in color correlation space. K R as green (G) minus red and K B as G minus blue are a color correlation space of low-pass signal, and luminance component contains most of the information of a full-color image. Thus, K R/K B plus luminance component is considered as a color correlation space for regularization. Experimental results show that our algorithm is efficient in removing visual artifact, preserving the edges of image with high-peak signal-to-noise ratio, and satisfying visual effect. View full abstract»

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  • Comments on "Semi-Blind Channel Estimation and Equalization for MIMO Space - Time Coded OFDM

    Page(s): 3513
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (55 KB) |  | HTML iconHTML  

    For original paper see ibid., vol.53, no.2, p.363-374, Feb. 2006. A semiblind channel estimation scheme of the multiple-input-multiple-output space-time coded orthogonal frequency-division multiplexing system was proposed in the aforementioned paper for either real or complex with symmetric signals. We point out that this scheme cannot work correctly for complex signal scenario. View full abstract»

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  • Convergence Analysis of a Class of Nonsmooth Gradient Systems

    Page(s): 3514 - 3527
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB) |  | HTML iconHTML  

    In this paper, we present new results on convergence of a class of nonlinear dynamical systems modeled by the gradients of nonsmooth cost functions. This class of systems arises from neural-network research and can be regarded as a generalization of existing neural-network models. Using the recently developed Lstrokojasiewicz gradient inequality, the convergence analysis of this gradient-like differential inclusion is given. Without assuming the smoothness of the cost function or analyticity of the activation function, we prove the output convergence of the differential system. In addition, for the piecewise analytic activation function with positive first-order derivative, we prove the state convergence. Furthermore, we also discuss the relationship between the convergence rate and the location of terminal limit point. Numerical examples are provided to illustrate the theoretical results and present the goal-seeking capability of the systems. View full abstract»

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  • Lyapunov Method and Convergence of the Full-Range Model of CNNs

    Page(s): 3528 - 3541
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (964 KB) |  | HTML iconHTML  

    This paper develops a Lyapunov approach for studying convergence and stability of a class of differential inclusions termed differential variational inequalities (DVIs). The DVIs describe the dynamics of a general system evolving in a compact convex subset of the state space. In particular, they include the dynamics of the full-range (FR) model of cellular neural networks (CNNs), which is characterized by hard-limiter nonlinearities with vertical segments in the i-v characteristic. The approach is based on the following two main tools: 1) a set-valued derivative, which enables to compute the evolution of a Lyapunov function along the solutions of the DVIs without involving integrations, and 2) an extended version of LaSalle's invariance principle, which permits to study the limiting behavior of the solutions with respect to the invariant sets of the DVIs. Then, this paper establishes conditions for convergence (complete stability) of DVIs in the presence of multiple equilibrium points (EPs), global asymptotic stability (GAS), and global exponential stability (GES) of the unique EP. These conditions are applied to investigate convergence, GAS, and GES for FR-CNNs and some extended classes of FR-CNNs. It is shown that, by means of the techniques developed in this paper, the analysis of convergence and stability of FR-CNNs is no more difficult than that of the standard (S)-CNNs. In addition, there are significant cases, such as the symmetric FR-CNNs and the nonsymmetric FR-CNNs with a Lyapunov diagonally stable matrix, where the proof of convergence or global stability is much simpler than that of the S-CNNs. View full abstract»

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  • Eigenfilter Approach to the Design of One-Dimensional and Multidimensional Two-Channel Linear-Phase FIR Perfect Reconstruction Filter Banks

    Page(s): 3542 - 3551
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1569 KB) |  | HTML iconHTML  

    We present an eigenfilter-based approach for the design of two-channel linear-phase FIR perfect-reconstruction (PR) filter banks. This approach can be used to design 1-D two-channel filter banks, as well as multidimensional nonseparable two-channel filter banks. Our method consists of first designing the low-pass analysis filter. Given the low-pass analysis filter, the PR conditions can be expressed as a set of linear constraints on the complementary-synthesis low-pass filter. We design the complementary-synthesis filter by using the eigenfilter design method with linear constraints. We show that, by an appropriate choice of the length of the filters, we can ensure the existence of a solution to the constrained eigenfilter design problem for the complementary-synthesis filter. Thus, our approach gives an eigenfilter-based method of designing the complementary filter, given a ldquopredesignedrdquo analysis filter, with the filter lengths satisfying certain conditions. We present several design examples to demonstrate the effectiveness of the method. View full abstract»

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  • Energy-Efficient Low-Complexity CMOS Pulse Generator for Multiband UWB Impulse Radio

    Page(s): 3552 - 3563
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1905 KB) |  | HTML iconHTML  

    This paper presents an energy-efficient low-complexity pulse-generator design technique for multiband impulse-radio ultrawide-band (IR-UWB) system in 0.18-mum CMOS technology. The short pulses are generated based on the on/off switching operation of an oscillator with subband switching functionality, which is mandatory for multiband IR-UWB systems. The relation between the oscillator switching operation and the resulting output pulse envelope, which determines pulse spectral characteristics, is analyzed, and the design guidelines for topology and component values are presented. Measurements show the output pulses with the duration of 3.5 ns, which corresponds to 520-MHz bandwidth. The output pulse spectrum centered at 3.8 GHz fully complies with the Federal Communication Commission spectral mask with more than 25 dB of sidelobe suppression without the need for additional filtering. Thus, the low-complexity pulse generator can maintain its simplicity for low cost with core chip size of 0.3 mm2. The pulse generator shows an excellent energy efficiency with average energy dissipation of 16.8 pJ per pulse from 1.5-V supply. The proposed pulse generator is best suited for energy-detection IR-UWB systems. View full abstract»

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  • Antenna-in-Package and Transmit–Receive Switch for Single-Chip Radio Transceivers of Differential Architecture

    Page(s): 3564 - 3570
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1512 KB) |  | HTML iconHTML  

    A fully differential architecture from the antenna to the integrated circuit is proposed for radio transceivers in this paper. The physical implementation of the architecture into truly single-chip radio transceivers is described for the first time. Two key building blocks, the differential antenna and the differential transmit-receive (T-R) switch, were designed, fabricated, and tested. The differential antenna implemented in a package in low-temperature cofired-ceramic technology achieved impedance bandwidth of 2%, radiation efficiency of 84%, and gain of 3.2 dBi at 5.425 GHz in a size of 15 x 15 x 1.6 mm3. The differential T-R switch in a standard complementary metal-oxide-semiconductor technology achieved 1.8-dB insertion loss, 15-dB isolation, and 15-dBm 1-dB power compression point (P 1dB) without using additional techniques to enhance the linearity at 5.425 GHz in a die area of 60 x 40 mum2. View full abstract»

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  • A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators

    Page(s): 3571 - 3581
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB) |  | HTML iconHTML  

    In this paper, a bandpass analog-to-digital converter (ADC) based on time-interleaved oversampled ADC is introduced. Unlike previous delta-sigma bandpass ADCs that require accurate digital-to-analog converters and high-speed analog circuits, the proposed architecture provides bandpass function by time-interleaving first-order voltage-controlled-oscillator (VCO)-based ADCs. The use of VCO-based ADC has the advantage that its resolution is determined by the time resolution rather than the voltage resolution, thus making it attractive for future low-voltage CMOS processes. The performance of the proposed ADC is theoretically analyzed and simulated in ideal condition, as well as in nonideal condition, in the presence of nonlinearity, sampling clock jitter, and mismatch. View full abstract»

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  • Performance Enhancement of Switched-Current Technique Using Subthreshold MOS Operation

    Page(s): 3582 - 3592
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (715 KB) |  | HTML iconHTML  

    The general performance of class AB switched currents (SI) is analyzed using the general MOS equations valid for all regions of operation. Using a figure-of-merit combining speed, dynamic range, and power consumption, the overall performance is shown to improve progressively as the SI memory transistors' operating region is moved from strong inversion to moderate and then weak inversion. The analysis is validated first by experiment using transistor arrays and then by simulation using 0.35-mum, 0.18-mum, and 90-nm CMOS process data. After discussing nonideal behavior of the weak inversion memory cell, the following two practical designs are described: a cascoded class AB memory at 1.25-V supply in the 3.3-V 0.35-mum process and a two-step sampling class AB memory at 0.6-V supply in the 1.8-V 0.18-mum process, and each demonstrates good performance. View full abstract»

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  • Measurement and Reduction of ISI in High-Dynamic-Range 1-bit Signal Generation

    Page(s): 3593 - 3606
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (702 KB) |  | HTML iconHTML  

    This paper studies spurious signals produced by the nonlinear interaction of the previous output symbols of a digital-to-analog converter (DAC) with its current symbol. This effect, called nonlinear intersymbol interference (ISI), significantly degrades the spurious-free dynamic range of most high-speed DACs. Many papers have been devoted to suppressing level inaccuracies in multibit DACs. However, even when all levels are accurate, nonlinear ISI causes significant spurious output. This paper presents a simple and very general model for nonlinear ISI and uses it to design binary signals that can both measure and suppress the spurious tones that arise in a single-bit DAC. While the analysis in this paper is based on a 1-bit DAC, extension to multibit DACs is possible, since a multibit DAC is merely a collection of 1-bit DACs and exhibits the same nonlinear effects. Experimental verification is presented for three different hardware setups. Measurements first establish the presence of the spurious tones in the hardware, as predicted by the model, and then show how the spur level can be reduced by as much as 22 dB. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras