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Electron Devices, IEEE Transactions on

Issue 12 • Date Dec. 2008

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  • Table of contents

    Publication Year: 2008 , Page(s): C1 - 3322
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  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2008 , Page(s): C2
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  • Kudos to our reviewers

    Publication Year: 2008 , Page(s): 3323
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  • Golden Report Selections T-ED

    Publication Year: 2008 , Page(s): 3324 - 3345
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  • Confidentiality of the review process

    Publication Year: 2008 , Page(s): 3346
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  • Novel TCAD-Oriented Definition of the off-State Breakdown Voltage in Schottky-Gate FETs: A 4H–SiC MESFET Case Study

    Publication Year: 2008 , Page(s): 3347 - 3353
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (905 KB) |  | HTML iconHTML  

    Physics-based breakdown voltage optimization in Schottky-barrier power RF and microwave field-effect transistors as well as in high-speed power-switching diodes is today an important topic in technology computer-aided design (TCAD). off-state breakdown threshold criteria based on the magnitude of the Schottky-barrier leakage current can be directly applied to TCAD; however, the results obtained are not accurate due to the large uncertainty in the Schottky-barrier parameters and models arising above all in advanced wide-gap semiconductors and to the need of performing high-temperature simulations to improve the numerical convergence of the model. In this paper, we suggest a novel off-state breakdown criterion, based on monitoring the magnitude (at the drain edge of the gate) of the electric field component parallel to the current density. The new condition is shown to be consistent with more conventional definitions and to exhibit a significantly reduced sensitivity with respect to physical parameter variations. View full abstract»

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  • Punchthrough-Voltage Enhancement of AlGaN/GaN HEMTs Using AlGaN Double-Heterojunction Confinement

    Publication Year: 2008 , Page(s): 3354 - 3359
    Cited by:  Papers (22)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (687 KB) |  | HTML iconHTML  

    In this paper, we present an enhancement of punchthrough voltage in AlGaN/GaN high-electron-mobility-transistor devices by increasing the electron confinement in the transistor channel using an AlGaN buffer-layer structure. An optimized electron confinement results in a scaling of punchthrough voltage with device geometry and a significantly reduced subthreshold drain leakage current. These beneficial properties are pronounced even further if gate-recess technology is applied for device fabrication. Physical-based device simulations give insight in the respective electronic mechanisms. View full abstract»

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  • High-Voltage 4H-SiC Bipolar Junction Transistors With Epitaxial Regrowth of the Base Contact

    Publication Year: 2008 , Page(s): 3360 - 3366
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (793 KB) |  | HTML iconHTML  

    High-voltage (4-6 kV) 4H-SiC-based bipolar junction transistors were designed, fabricated, and characterized. Various design and process optimization techniques to improve the on state and the forward blocking performance of these devices were studied and incorporated. Using the conventional base contact implantation process, devices with blocking voltages up to 4 kV and specific on-resistance (R on, sp) values higher than the unipolar limit (37 mOmegamiddotcm2), with a current gain of ten in the active region, were experimentally demonstrated. A novel selective growth of p-contact-based process was developed and implemented. This, coupled with improvements in the termination design, resulted in enhancing the blocking voltage capability to 6 kV while simultaneously lowering the R on, sp to below the unipolar limit (28 mOmegamiddotcm2 and current gain of four in the active region), for the same starting material. Evidence for the presence of conductivity modulation (for the first time) in high-voltage SiC BJTs was also shown experimentally. View full abstract»

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  • Timing Randomly Spaced Events Using the Threshold-Voltage Shift in Disordered Semiconductors

    Publication Year: 2008 , Page(s): 3367 - 3374
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (598 KB) |  | HTML iconHTML  

    This paper discusses the concept of using the threshold-voltage shift in disordered-semiconductor-based thin- film transistors to measure the time of occurrence of randomly spaced events of interest. We call the experimental circuit an "analog clock." The analog clock is shown to be accurate while, at the same time, being simple in design using just one transistor. View full abstract»

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  • Thermal Study of High-Power Nitride-Based Flip-Chip Light-Emitting Diodes

    Publication Year: 2008 , Page(s): 3375 - 3382
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1039 KB) |  | HTML iconHTML  

    This paper presents a chip-level thermal study of high-power nitride-based flip-chip (FC) light-emitting diodes (LEDs). In order to understand the thermal performance of the high-power FC LEDs thoroughly, a quantitative parametric analysis of the thermal dependence on the chip contact area, bump configuration, and bump defects was performed by finite-element model (FEM) numerical simulation and thermal infrared (IR) microscopy testing, respectively. FEM numerical simulation results proved that the optimized bump configuration design was essential to get a uniform temperature distribution in the active layer and improve the thermal performance of the FC LED. IR microscopy testing results recognized that bump defects formed in the LED chip solder processing would lead to surface hot spots around the vicinity of these bump defects, particularly under high-current working conditions. In addition, a light-emitting dark zone was also observed in the optical field for FC LEDs with bump defects. In summary, optimized LED FC bump configuration design and good bonding quality in the chip bonding process are proved to be critical for improving the thermal performance and extending the operating longevity of high-power FC LEDs. View full abstract»

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  • Low-Noise In-Pixel Comparing Active Pixel Sensor Using Column-Level Single-Slope ADC

    Publication Year: 2008 , Page(s): 3383 - 3388
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (663 KB) |  | HTML iconHTML  

    A conventional active pixel sensor (APS) uses a source follower (SF) in a pixel as a buffer. This SF is one of the major causes of nonlinearity, sensitivity degradation, and pixel readout noise. The proposed in-pixel comparing APS uses pixel transistors as a part of comparator for a single-slope ADC instead of using them as an SF. The prototype sensor was fabricated using a 0.35-mum 2P3M CMOS process. Experimental results show 15-times linearity improvement, 26% sensitivity enhancement, and 33% noise reduction over the conventional APS. View full abstract»

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  • New Reset Waveform for a Large-Sustain-Gap Structure in an Alternating Current Plasma Display Panel

    Publication Year: 2008 , Page(s): 3389 - 3395
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1095 KB) |  | HTML iconHTML  

    A new reset waveform for a large-sustain-gap structure in an ac plasma display panel is proposed. In the driving of a large-sustain-gap structure with a conventional ramp reset waveform, we cannot avoid the condition of an address electrode being a cathode, which causes lots of trouble in stabilizing the reset discharge. To resolve these problems, a square pulse instead of the conventional rising-ramp pulse is used. In order to stabilize the strong discharge in which the address electrode becomes a cathode, a priming discharge between the address (anode) and scan (cathode) electrodes is made prior to making a strong discharge between the address (cathode) and scan (anode) electrodes. With this scheme, a minimum address voltage of 60 V when the sustain gaps are 250 and 350 mum, respectively, is obtained. However, the contrast ratio using the square reset pulse is lower than that using the conventional ramp pulse. To improve the contrast ratio, the reset waveforms in each subfield are replaced by selective erase waveforms except for the first subfield. In the case of nonselective reset waveform, the background luminance is 19.4 cd/m2, whereas the background luminance of 2.4 cd/m2 is obtained with selective reset waveform. View full abstract»

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  • CMOS Avalanche Photodiode Embedded in a Phase-Shift Laser Rangefinder

    Publication Year: 2008 , Page(s): 3396 - 3401
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (879 KB) |  | HTML iconHTML  

    This paper presents the design and the characterization of a CMOS avalanche photodiode (APD) working as an optoelectronic mixer. The P+N photodiode has been implemented in a commercial 0.35-mum CMOS technology after optimization with SILVACO. The surface of the active region is 3.78 middot10-3 cm2. An efficient guard-ring structure has been created using the lateral diffusion of two n-well regions separated by a gap of 1.2 mum. When biased at -2 V, the best responsitivity Slambda APD = 0.11 A/W is obtained at lambda = 500 nm. This value can easily be improved by using an antireflection coating. At lambda = 472 nm, the internal gain is about 75 at -6 V and 157 at -7 V. When biased at -6 V, the APD achieves a dark current of 128 muA middotmm-2 and an excess noise factor F = 20. Then, the APD is successfully used as an optoelectronic mixer to improve the signal-to-noise ratio of a low-voltage embedded phase-shift laser rangefinder. View full abstract»

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  • Near-100% Quantum Efficiency of Delta Doped Large-Format UV-NIR Silicon Imagers

    Publication Year: 2008 , Page(s): 3402 - 3406
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (262 KB) |  | HTML iconHTML  

    We have demonstrated a back surface process for back-illuminated high-purity p-channel charge-coupled devices (CCDs), enabling broadband coverage from the ultraviolet to near infrared (NIR). The process consists of the formation of a delta layer followed by a double layer antireflection (AR) coating. The process is performed below 450degC and is applied to fully fabricated CCDs with aluminum metallization. The delta doping process was demonstrated on 1 k times 1 k and 2 k times 4 k CCDs, which were found to exhibit low dark current and near reflection-limited quantum efficiency. Two broadband AR coatings were developed to cover the UV-visible and visible-NIR bands. These coatings consist of a double layer of SixNy and SiOx deposited by plasma enhanced chemical vapor deposition onto the back surface of a delta doped CCD. The thicknesses of the coating layers are adjusted for the desired bandpass. View full abstract»

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  • New Address-While-Display Driving Method for High Contrast Ratio and Wide Operation Margin PDP Using Short Ramp Reset (SRR) and Short Pulse Erase (SPE) Schemes

    Publication Year: 2008 , Page(s): 3407 - 3413
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1217 KB) |  | HTML iconHTML  

    We propose a new address-while-display (AWD) driving method for a plasma display panel to obtain a high contrast ratio and a wide operation margin, which is composed of a short ramp reset (SRR) period, a short erase period, a sustain period, and an address period as the basic units. The SRR pulse and the short pulse erase period make it possible to obtain a wide operating voltage margin and minimize the background luminance by redistributing the wall charges in a short initialization time between the address and the scan electrode. As a result, a high darkroom contrast ratio of 10 000 :1 could be achieved with a wide operating voltage margin of 40 V for a stable address. View full abstract»

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  • Mobility and Dielectric Quality of 1-nm EOT HfSiON on Si(110) and (100)

    Publication Year: 2008 , Page(s): 3414 - 3420
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB) |  | HTML iconHTML  

    In this paper, we study the mobility and dielectric quality of MOSFETs with 1-nm Equivalent Oxide Thickness (EOT) grown on substrates with different crystallographic orientations: (100) and (110). Measurement techniques based on RF split CVs (150 MHz) on short-channel devices (down to 80 nm) are used to extract the electrical parameters. Despite the different oxidation growth rates expected by changing the substrate orientation, we obtain similar EOT values even for thin dielectrics (1 nm). Further identical gate overlaps are found regardless of the substrate orientation. The mobility in (110) substrate shows a large improvement for p-MOS. This improvement is independent of the EOT (down to 1 nm) and the length scaling. Although larger interface states were observed by charge pumping for the (110) devices, low-temperature mobility study suggests that the remote charge scattering, and therefore, the gate stack quality is the same. View full abstract»

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  • Exploring the Capability of Multifrequency Charge Pumping in Resolving Location and Energy Levels of Traps Within Dielectric

    Publication Year: 2008 , Page(s): 3421 - 3431
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (646 KB) |  | HTML iconHTML  

    Multifrequency charge-pumping (MFCP) experiments have been used by many groups to profile the locations and the energy levels of bulk traps within high-kappa gate dielectric stack of MOS transistors. Since the measurements involve easy generalization of the classical CP technique, the interpretation of the data has sometimes been based on uncritical generalization of classical CP theory or a simplified numerical model that does not capture the complexity and nuances of the dynamics of occupation of dielectric traps. In this paper, we develop a rigorous numerical model of MFCP technique and encapsulate/interpret the results using an intuitively simple analytical formula. Consistent with some earlier reports, we observe that MFCP experiment scans a limited region of traps within the dielectric stack. Although the degree of trap response in MFCP is a (nonintuitive) function of parameters like rise/fall time, frequency, temperature, and pulse levels, we show that only a certain combination of parameters is sufficiently orthogonal to allow unambiguous back-extraction of the trap profile. View full abstract»

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  • Reliability of Strained-Si Devices With Post-Oxide-Deposition Strain Introduction

    Publication Year: 2008 , Page(s): 3432 - 3441
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (494 KB) |  | HTML iconHTML  

    To assess the impact of strain on negative bias temperature instability (NBTI), systematic studies were performed on devices with polycrystalline-Si/SiON as well as deposited metal gate/high-kappa and FUSI/high-kappa gate stacks. The effects of compressive stress, which acts as performance booster for PMOS devices, were studied, with strain introduced by stressor layers as well as SiGe source/drain techniques. Care was taken to account for side effects of processing steps used to introduce the strain, such as changes on threshold voltage or capacitance equivalent thicknesses, in order to obtain a fair evaluation of the intrinsic effect of strain on NBTI. NBTI measurements were complemented by charge pumping and noise measurements to obtain a comprehensive understanding of defects present and of their generation under stress. In addition, nanobeam diffraction strain measurements, as well as curvature mass simulations, were performed in order to investigate the impact of strain on carrier mobility in the vertical direction. Our studies showed consistently that there is no significant degradation of intrinsic NBTI behavior due to process-induced strain. View full abstract»

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  • Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs

    Publication Year: 2008 , Page(s): 3442 - 3449
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (275 KB) |  | HTML iconHTML  

    In this paper, analytical models of subthreshold current and slope for asymmetric four-terminal double-gate (DG) MOSFETs are presented. The models are used to study the subthreshold characteristics with asymmetry in gate oxide thickness, gate material work function, and gate voltage. A model for the subthreshold behavior of three-terminal DG MOSFETs is also presented. The results of the models show excellent match with simulations using MEDICI. The analytical models provide physical insight which is helpful for device design. View full abstract»

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  • A Pearson Effective Potential for Monte Carlo Simulation of Quantum Confinement Effects in nMOSFETs

    Publication Year: 2008 , Page(s): 3450 - 3458
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB) |  | HTML iconHTML  

    An original Pearson effective potential (PEP) model for including quantization effects in the simulation of nanoscale nMOSFETs has been introduced in a Monte Carlo (MC) simulator. The PEP correction properly accounts for quantum confinement effects in bulk-, single-, and double-gate silicon-on-insulator nMOS capacitors and nanoscale nMOSFETs devices. The results obtained from semiclassical, PEP-corrected, and multisubband MC approaches are reported and compared for a double-gate nMOSFET with a channel length L C=10 nm and a silicon film thickness T Si=5 nm at low and high drain voltages. Excellent agreements are obtained between PEP-corrected and multisubband MC methods on both electrical characteristics and microscopic quantities. Finally, the impact of quantum confinement effects on drive current is evaluated in double-gate structures over a large range of channel length and silicon film thickness. View full abstract»

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  • Design and Realization of a Fully On-Chip High- Q Resonator at 15 GHz on Silicon

    Publication Year: 2008 , Page(s): 3459 - 3466
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (907 KB) |  | HTML iconHTML  

    We develop and demonstrate an on-chip resonator working at 15 GHz with a high quality factor (Q-factor) of 93.81 while only requiring a small chip size of 195 mum times195 mum on Si by using our new design methodology. In our design, unlike previous approaches, we avoid the need for any external capacitance for tuning; instead, we utilize the film capacitance as the capacitor of the LC tank circuit and realize a fully on-chip resonator that shows a strong transmission dip of >30 db on resonance as required for telemetric-sensing applications. We present the design, theory, methodology, microfabrication, experimental characterization, and theoretical analysis of these resonators. We also demonstrate that the experimental results are in excellent agreement with the theoretical (both analytical and numerical) results. Based on our proof-of-concept demonstration, such high-Q on-chip resonators hold great promise for use in transmissive telemetric sensors. View full abstract»

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  • Three-Dimensional Closed-Form Model for Potential Barrier in Undoped FinFETs Resulting in Analytical Equations for V_{T} and Subthreshold Slope

    Publication Year: 2008 , Page(s): 3467 - 3475
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (477 KB) |  | HTML iconHTML  

    An analytical approach for modeling the electrostatic potential in nanoscale undoped FinFETs is derived. This method uses a 2-D solution for this potential within a double-gate FET and takes into account the top gate electrode as the third dimension by applying the conformal mapping technique. Herewith, an analytical closed-form model for the height of the potential barrier below threshold is defined which includes 3-D effects. From that, models for subthreshold slope and threshold voltage of nanoscale triple-gate FETs are derived. The results are in good agreement with numerical device simulation results and measurements for channel lengths down to 20 nm. View full abstract»

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  • Floating-Gate Nonvolatile Memory With Ultrathin 5-nm Tunnel Oxide

    Publication Year: 2008 , Page(s): 3476 - 3481
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (761 KB) |  | HTML iconHTML  

    Reliability results of floating-gate (FG) memory using 5-nm tunnel oxides in mature (0.25 mum) to advanced (65 nm) logic processes from multiple foundries are reported. Good intrinsic retention is seen across the process nodes studied and for gate oxides as thin as 4.8 nm. With differential memory cells, we also demonstrate promising reliability results with respect to program-cycle-induced tail bits. We conclude that it is possible to develop a small-bit-count FG nonvolatile memory (NVM) array using 5-nm oxide, enabling embedded logic NVM in advanced CMOS processes with no additional masks or processing steps. View full abstract»

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  • Nano-Electro-Mechanical Nonvolatile Memory (NEMory) Cell Design and Scaling

    Publication Year: 2008 , Page(s): 3482 - 3488
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (831 KB) |  | HTML iconHTML  

    The design and scalability of a nano-electro- mechanical memory (NEMory) cell are investigated via analytical modeling and finite element analysis (FEA) simulation. Proportionate scaling of all the cell dimensions provides for improved storage density together with low operating voltages and fast program/erase times. From FEA simulation, a 75-nm-long aluminum cantilever-beam NEMory cell is expected to have sub-1-ns erase and program times for sub-l-V operation. Because there are practical limits to beam and air-gap thickness scaling, it will be difficult to achieve low-voltage operation for very short beams (Lbeam < 50 nm), unless a beam material with a low Young's modulus is used. Fracture strain imposes a fundamental limit for beam-length scaling. Thus, a high fracture-strain beam material is desirable to extend NEMory scalability. View full abstract»

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  • Characteristics of \hbox {HfO}_{2} /Poly-Si Interfacial Layer on CMOS LTPS-TFTs With \hbox {HfO}_{2} Gate Dielectric and \hbox {O}_{2} Plasma Surface Treatment

    Publication Year: 2008 , Page(s): 3489 - 3493
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (977 KB) |  | HTML iconHTML  

    In this paper, high-performance complementary-metal-oxide-semiconductor low-temperature polycrystalline-silicon thin-film transistors (CMOS LTPS-TFTs) with HfO2 gate dielectric are fabricated on one wafer for the first time. Low threshold voltage and excellent subthreshold swing can be achieved simultaneously for N- and P-channel LTPS-TFTs without hydrogenation. In addition, the impacts of the HfO2 /poly-Si interfacial layer on N- and P-channel LTPS-TFTs are also specified. In order to enhance the characteristics of HfO2 LTPS-TFT further, oxygen plasma surface treatment is employed to improve the interface quality and passivate the defects of channel grain boundaries, thus increasing the carrier mobility and reducing the phonon scattering. The CMOS LTPS-TFTs with HfO2 gate dielectric and oxygen plasma treatment would be suitable for the application of system-on-panel. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego