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Advanced Packaging, IEEE Transactions on

Issue 4 • Date Nov. 2008

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  • Table of contents

    Publication Year: 2008 , Page(s): C1 - 661
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    Freely Available from IEEE
  • IEEE Transactions on Advanced Packaging publication information

    Publication Year: 2008 , Page(s): C2
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  • Foreword Special Section on Electrical Performance Analysis and Simulation of Interconnects, Packages and Devices Composing Electronic Systems for High-Performance Applications

    Publication Year: 2008 , Page(s): 662 - 663
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  • Modal Vector Fitting: A Tool For Generating Rational Models of High Accuracy With Arbitrary Terminal Conditions

    Publication Year: 2008 , Page(s): 664 - 672
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (506 KB) |  | HTML iconHTML  

    This paper introduces a new approach for rational macromodeling of multiport devices that ensures high accuracy with arbitrary terminal conditions. This is achieved by reformulating the vector fitting (VF) technique to focus on eigenpairs rather than matrix elements. By choosing the least squares (LS) weighting equal to the inverse of the eigenvalue magnitude, the modal components are fitted with a relative accuracy criterion. The resulting modal vector fitting (MVF) method is shown to give a major improvement in accuracy for cases with a high ratio between the largest and smallest eigenvalue, although it is computationally more costly than VF. It is also shown how to utilize the impedance characteristics of the adjacent network in the fitting process. The application of MVF is demonstrated for a two-conductor stripline, a coaxial cable, and a transformer measurement. We also show a simplified procedure which achieves similar results as MVF if the admittance matrix can be diagonalized by a constant transformation matrix. The extracted model is finally subjected to passivity enforcement by the modal perturbation method, which makes use of a similar LS formulation as MVF for the constrained optimization problem. View full abstract»

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  • A Comparative Study of Passivity Enforcement Schemes for Linear Lumped Macromodels

    Publication Year: 2008 , Page(s): 673 - 683
    Cited by:  Papers (42)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1292 KB) |  | HTML iconHTML  

    This paper presents a comparative study of several passivity enforcement schemes for linear lumped macromodels. We consider three main classes of algorithms. First class is represented by those methods based on a direct enforcement of positive/bounded real lemma constraints via convex optimization. Second class includes those algorithms that enforce the passivity constraints at discrete frequency samples. These schemes are here formulated as second-order cone programs in order to optimize performance. Finally, we consider algorithms based on Hamiltonian eigenvalue perturbation. These three classes are applied to a significant set of benchmark examples, essentially various kinds of high-speed interconnects and packages, with the aim of comparing their performance in terms of accuracy, efficiency, applicability, and robustness. These examples are specifically selected in order to be critical for one or more algorithms, in terms of excessive accuracy degradation, computational complexity, or even lack of convergence. One important result is that carefully designed weighting schemes may dramatically improve performance for all considered algorithm classes. View full abstract»

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  • Frequency Domain Analysis of Transmission Zeroes on High-Speed Interconnects in the Presence of an Orthogonal Metal Grid Underlayer

    Publication Year: 2008 , Page(s): 684 - 691
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (846 KB) |  | HTML iconHTML  

    This paper addresses the topic of high-speed interconnects in high density systems [systems on chip (SoCs), systems in package (SiPs), systems on package (SoPs), and multichip modules (MCMs)]. These microstrip or coplanar lines have, often, an underlayer of orthogonal metal grids liable to affect transmission characteristics. The characterization proposed in this paper relies on S -parameter measurements and electromagnetic simulations. The grids under study are of two kinds: grounded (CC) and floating (CO). In both cases, the signal is distorted in the time domain further to the occurrence of transmission zeroes whose position depend mainly on the grid length and, of course, on the grid charge, i.e., CC or CO. In order to easily estimate this position, we developed a simple equivalent circuit model and validated it by measurements and electromagnetic simulations. Then it was used to develop a set of expressions enabling one to analytically pinpoint the location of transmission zeroes in the frequency domain, while remaining valid for any underlayer of orthogonal metal lines or grids. View full abstract»

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  • Performance Comparison Between Metallic Carbon Nanotube and Copper Nano-Interconnects

    Publication Year: 2008 , Page(s): 692 - 699
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB) |  | HTML iconHTML  

    This paper addresses the problem of scaling interconnects to nanometric dimensions in future very-large-scale integration applications. Traditional copper interconnects are compared to innovative interconnects made by bundles of metallic carbon nanotubes. A new model is presented to describe the propagation of electric signals along carbon nanotube (CNT) bundles, in the framework of the classical transmission line theory. A possible implementation of a future scaled microstrip based on CNT bundle is analyzed and compared to a conventional microstrip. View full abstract»

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  • Locally-Stable Macromodels of Integrated Digital Devices for Multimedia Applications

    Publication Year: 2008 , Page(s): 700 - 710
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (649 KB) |  | HTML iconHTML  

    This paper addresses the development of accurate and efficient behavioral models of digital integrated circuits for the assessment of high-speed systems. Device models are based on suitable parametric expressions estimated from port transient responses and are effective at system level, where the quality of functional signals and the impact of supply noise need to be simulated. A potential limitation of some state-of-the-art modeling techniques resides in hidden instabilities manifesting themselves in the use of models, without being evident in the building phase of the same models. This contribution compares three recently-proposed model structures, and selects the local-linear state-space modeling technique as an optimal candidate for the signal integrity assessment of data links. In fact, this technique combines a simple verification of the local stability of models with a limited model size and an easy implementation in commercial simulation tools. An application of the proposed methodology to a real problem involving commercial devices and a data-link of a wireless device demonstrates the validity of this approach. View full abstract»

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  • Improving Behavioral IO Buffer Modeling Based on IBIS

    Publication Year: 2008 , Page(s): 711 - 721
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1480 KB) |  | HTML iconHTML  

    High level behavioral modeling is widely used in lieu of low level transistor models to ascertain the behavior of input/output (IO) drivers and receivers. The input output buffer information specification (IBIS) is one of the most widely used methodologies to model IO drivers as it satisfies the basic requirements of a behavioral model such as IP protection, simple structure, fast simulation time, and reasonable accuracy. As driver technology gets increasingly complicated and rise time of input signal gets increasingly smaller, important considerations such as simultaneous switching noise (SSN) becomes a major consideration when simulating multiple IO drivers in the integrated circuit. Unfortunately, IBIS falls short of becoming a complete IO behavioral model when simulating for SSN. This paper addresses the problem by assessing what is missing in IBIS. A method is presented for compensating for the missing information by complimenting the IBIS model with a black box that is simulator independent, without compromising with the speed that IBIS enjoys over the transistor models. View full abstract»

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  • Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Designs

    Publication Year: 2008 , Page(s): 722 - 730
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1397 KB) |  | HTML iconHTML  

    Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in SPICE simulations, however, results in long simulation time. Innovative simulation techniques based on a statistical simulation framework have been recently introduced to cosimulate deterministic and random jitter effects efficiently. This paper presents new improvements on this statistical simulation framework. In particular, we introduce an accurate jitter modeling technique which accounts for bounded jitter with arbitrary spectrum in addition to Gaussian jitter. We also present a rigorous approach to model duty cycle distortion (DCD). A number of I/O systems are considered as examples to validate the proposed modeling methodology. View full abstract»

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  • Controlled Intersymbol Interference Design Techniques of Conventional Interconnect Systems for Data Rates Beyond 20 Gbps

    Publication Year: 2008 , Page(s): 731 - 740
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2141 KB) |  | HTML iconHTML  

    This paper presents a new design technique of high-speed interconnects with controlled intersymbol interference (ISI) to create efficient signaling over a band-limited channel. Performance of high-speed electrical links is limited by conductor loss, dielectric dispersion, and reflections in the board, package, and connector. These nonidealities result in significant ISI. In current systems, the effect of ISI is either mitigated through complex equalization, signal conditioning, and coding techniques, or through costly impedance control and manufacturing processes. In the proposed approach, instead of eliminating ISI, we shape the response of the channel into a set of channel characteristics with controlled ISI using simple passive structures in the board and the package. The resulting controlled ISI is exploited at the transmitter and receiver to simplify the architecture of the system and to achieve high data rates. The techniques to design interconnects with controlled ISI are reasonably simple to implement in conventional interconnect technologies. Simulation examples are given to demonstrate the validity and advantages of the design technique using duobinary and analog multitone (AMT) signaling methods. View full abstract»

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  • Multiple Edge Responses for Fast and Accurate System Simulations

    Publication Year: 2008 , Page(s): 741 - 748
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1054 KB) |  | HTML iconHTML  

    High-speed input/output (I/O) link performance is limited by random noise as well as signal integrity issues such as dispersion, reflections, and crosstalk. Hence, accurate prediction of system performance including these random and deterministic noise is crucial in high-speed link design. This paper presents a novel, fast, and accurate method to simulate the time-domain system response. The presented method calculates the system response using multiple edge responses (MER) based on linear superposition. Being able to take into account system nonlinearity more accurately, the presented method significantly improves simulation accuracy compared with the other published fast simulation techniques based on either single bit response (SBR) or double edge responses (DER), while at the same time maintaining equivalent numerical efficiency. Furthermore, peak distortion analysis, which is commonly used to find the worst-case data pattern based on SBR, is extended for DER and MER using dynamic programming. A multiphase worst-case data pattern approach is also introduced in this paper in order to determine the worst-case system performance under both timing and voltage consideration. View full abstract»

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  • Inductively Coupled Connectors and Sockets for Multi-Gb/s Pulse Signaling

    Publication Year: 2008 , Page(s): 749 - 758
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1211 KB) |  | HTML iconHTML  

    Multi-Gb/s pulse signaling is demonstrated with inductively coupled interconnects across packaging interfaces. This has application in realizing submillimeter pitch, true zero insertion force (ZIF) surface mount connectors, and sockets. The signaling data rate achieved in this system is from 1 to 8.5 Gbps, which depends on the 3-dB coupling frequency of the composite channel consisting of the inductive interconnections and the transmission lines. This paper presents the results of a set of experiments demonstrating this capability and describes the principles behind the design of inductively coupled sockets and connectors. View full abstract»

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  • Polymer-Waveguide-Based Board-Level Optical Interconnect Technology for Datacom Applications

    Publication Year: 2008 , Page(s): 759 - 767
    Cited by:  Papers (46)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2674 KB) |  | HTML iconHTML  

    On the basis of a realized 12times10 Gb/s card-to-card optical link demonstrator, the capabilities of a polymer-waveguide-based board-level optical interconnect technology are presented. The conception and realization of the modular building blocks required for this board-level optical interconnect technology are described in detail. In particular, we report on the fabrication and characterization of board-integrated optical low-loss polymer waveguides that are compatible with printed circuit board (PCB) manufacturing processes. We also explain our fully passive alignment technique, superseding time-consuming active positioning of components and connectors. To realize optical transceiver modules comprising vertical cavity surface emitting laser (VCSEL) arrays with laser drivers and photodetector arrays with transimpedance amplifiers (TIAs), a mass-production concept based on wafer-level processing has been elaborated and successfully implemented. View full abstract»

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  • PEEC Modeling of Dispersive and Lossy Dielectrics

    Publication Year: 2008 , Page(s): 768 - 782
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1888 KB) |  | HTML iconHTML  

    In this paper a general formulation is presented for the time-domain partial element equivalent circuit method in a general dispersive medium. The formulation is based on Debye and Lorentz models where the resulting model is passive. The incorporation of such models into a partial element equivalent circuit solver is described by both convolution techniques and equivalent circuits. The new circuit models can be applied in the frequency as well as the time domain. Numerical examples are given to validate the proposed formulation and to show that the proposed method is accurately capturing the physics of dispersive and lossy dielectrics. View full abstract»

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  • Interchannel Crosstalk Analysis in Parallel Optical Receiver up to 10 GHz

    Publication Year: 2008 , Page(s): 783 - 793
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1727 KB) |  | HTML iconHTML  

    This paper describes interchannel crosstalk in a parallel optical receiver at a data rate of 10 Gb/s and higher. Individual paths of interchannel crosstalk are categorized, and each path is investigated in detail with equivalent model measurements and simulations. At a frequency of 10 GHz, three individual package substrate crosstalk paths and supply and ground rails show a significant coupling level of higher than -22.9 dB. Regarding the quantity of coupled crosstalk, the supply and ground rails make the most significant crosstalk paths within the whole frequency range. In the last part of this paper, effective methods of isolating interchannel crosstalk at a single-channel speed of 10 Gb/s and higher are discussed. View full abstract»

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  • A Frequency Triplexer for Ultra-Wideband Systems Utilizing Combined Broadside- and Edge-Coupled Filters

    Publication Year: 2008 , Page(s): 794 - 801
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (610 KB) |  | HTML iconHTML  

    A fully integrated triplexer for multiband ultra-wideband radio is presented. The triplexer utilizes a microstrip network and three combined broadside- and edge-coupled filters. It is fully integrated in a printed circuit board with low requirements on the printed circuit board process tolerance. Three flat subbands in the frequency band 3.1-4.8 GHz have been achieved. The group delay variation within each 500-MHz subband was measured to be around 1 ns. A good agreement between simulation and measurement was obtained. View full abstract»

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  • Design and Manufacturing of Stretchable High-Frequency Interconnects

    Publication Year: 2008 , Page(s): 802 - 808
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (950 KB) |  | HTML iconHTML  

    The increasing number of biomedical applications for electronic systems have led to the need for stretchable electronics in order to significantly enhance the comfort of the user. This paper describes the design and manufacturing process of new stretchable high-frequency interconnects with meander-shaped conductors in a coplanar waveguide topology. The novel interconnects are produced based on laser-ablation of a copper foil, which is then embedded in a highly stretchable bio-compatible silicone material. Measurements on prototypes of the designed stretchable high-frequency interconnects revealed a maximal magnitude of -14 dB for the reflection coefficient and a minimal magnitude of -4 dB for the transmission coefficient in the frequency band up to 3 GHz. The influence of stretch on the performance of the high-frequency interconnects was analyzed using a stretch testing machine. The results showed that nor the magnitude, neither the phase of the transmission coefficient was influenced by elongations up to 20%. View full abstract»

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  • A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines

    Publication Year: 2008 , Page(s): 809 - 817
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1586 KB) |  | HTML iconHTML  

    A serpentine guard trace is proposed to reduce the peak far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines on printed circuit boards. The vertical sections of the serpentine guard increase the mutual capacitance without much changing the mutual inductance between the aggressor and victim lines. This reduces the difference between the capacitive and inductive couplings and hence the far-end crosstalk. Comparison with the no guard, the conventional guard, and the via-stitch guard shows that the serpentine guard gives the smallest values in both the peak far-end crosstalk voltage and the timing jitter. The time domain reflectometer (TDR) measurement shows that the peak far-end crosstalk voltage of serpentine guard is reduced to 44% of that of no guard. The eye diagram measurement of pseudo random binary sequence (PRBS) data shows that the timing jitter is also reduced to 40% of that of no guard. View full abstract»

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  • Full-Wave Analysis of Large-Scale Interconnects Using the Multilevel UV Method With the Sparse Matrix Iterative Approach (SMIA)

    Publication Year: 2008 , Page(s): 818 - 829
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2077 KB) |  | HTML iconHTML  

    Moving towards the goal of analyzing whole printed circuit boards (PCBs) and packages using full-wave electromagnetic (EM) methods, the multilevel UV method is applied to the method-of-moments (MoM) solution of the current on large-scale interconnects. The MoM solution uses the layered media Green's functions computed using the numerical modified steepest-descent path (NMSP) method, and is applied to the exterior layers of the interconnect structure. The sparse matrix iterative approach (SMIA) is used to speed up the solution of the iterative matrix solver. The iterative solver is also accelerated by using larger blocks in the block diagonal inverse preconditioner. With the multilevel UV method, a fast solution is presented for solving the current on large-scale interconnects on thin layered structures at high frequencies. We show an example of an interconnect structure that has horizontal dimensions of 12.675 lambda × 12.876 lambda with 24thinspace 848 current unknowns and an interconnect fractional area of approximately 31%. This problem takes a total of 21 min 20 s to solve for the current on the traces on a Pentium 3.2-GHz CPU with 4 GB of RAM. View full abstract»

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  • Full-Field 3-D Flip-Chip Solder Bumps Measurement Using DLP-Based Phase Shifting Technique

    Publication Year: 2008 , Page(s): 830 - 840
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1180 KB) |  | HTML iconHTML  

    The flip chip, a type of chip mounting used in semiconductor devices, has become one of the most popular innovations in the semiconductor packaging industry. The height of flip-chip solder bumps ranges from 20 to 140 mum with a required measurement accuracy of 2 mu m. Three-dimensional (3-D) measurement of flip-chip solder bumps is crucial to flip-chip manufacturing quality and process control. Currently, 3-D measurement systems for flip-chip solder bumps are mainly based on laser scanning techniques. However, they require a high implementation cost, and suffer from low inspection speed due to the physical line-scanning process. In this paper, a fast and cost-effective 3-D measurement system for flip-chip solder bumps is proposed. The proposed system is based on a phase shift technique, in which the phase is accurately shifted by a software-controlled grating using a digital light processing (DLP) unit that allows full-field measurement of a projected flip chip. The DLP unit can provide a higher fringe-contrast pattern at a faster changing time than a liquid crystal display (LCD) panel. Phase shift-based measurement systems require a calibrated system parameter, which is generally considered a fixed value in currently available methods. In this paper, adaptive parameter values, instead of a fixed value, are used to improve measurement accuracy. The proposed system also adopts a fringe-contrast thresholding to solve the pseudo-surface height problem for high reflective solder bumps and low reflective substrate in a flip chip. Experiments have shown that the 3-D measurement of flip-chip solder bumps is very efficient and effective with the proposed system. Computation time of the proposed 3-D measurement system for a 640 x 480 image that contains almost 500 solder bumps is less than 1 s, and measurement accuracy meets the required specification of 2 mum. View full abstract»

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  • Comprehensive Electromagnetic Modeling of On-Chip Switching Noise Generation and Coupling

    Publication Year: 2008 , Page(s): 841 - 854
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1340 KB) |  | HTML iconHTML  

    A comprehensive modeling methodology is presented for the investigation of on-chip noise generation and coupling due to power switching. The backbone of the methodology is an electromagnetic model for the on-chip portion of the power grid. This allows for the impact of the displacement current density and, hence, electromagnetic retardation, to be taken into account in the accurate modeling of the power grid behavior at picosecond switching speeds. In this manner, and through the interfacing of this model with an electromagnetic model for the package portion of the power grid, which is described in terms of a multiport rational matrix transfer function, the impact of package-chip electrical interactions on switching noise can be modeled with electromagnetic accuracy. The electromagnetic model for the power grid is complemented by a resistance-capacitance model for the semiconductor substrate, which is capable of modeling local substrate induced noise coupling between neighboring circuits. Finally, distributed resistance, inductance, capacitance and conductance circuits for signal wires are extracted and used to provide for a transmission line-based modeling of crosstalk and power grid induced signal degradation. Transient simulations using the proposed comprehensive model are carried out using a hybrid time-domain integration scheme which combines a SPICE-like engine for the analysis of all circuit netlists and the nonlinear drivers incorporated in the model with a numerical integration algorithm suitable for the expedient update of the state variables in the discrete electromagnetic model for the power grid. View full abstract»

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  • Integration and Characteristics of 40-Gb/s Electroabsorption Modulator Integrated Laser Module With a Driver Amplifier and Bias Tees

    Publication Year: 2008 , Page(s): 855 - 860
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (987 KB) |  | HTML iconHTML  

    Integration of a 40-Gb/s electroabsorption modulator integrated distributed feedback (DFB) laser (EML) module with a driver amplifier and bias tee was investigated. For the EML fabrication the selective area growth (SAG) technique was adopted for the first time. It is shown that, with the SAG technique, the 3-dB bandwidth of about 45 GHz was measured in the electrical to optical response, and the return loss (S11) of below -10 dB was achieved for up to 50 GHz . To integrate a bias tee within the module, a right-angle bent coplanar waveguide (CPW) was developed. The right-angle bent CPW was characterized with S11 of below - 10 dB for up to 35 GHz and insertion loss (S21) of about -1.4 dB for up to 40 GHz . The whole integrated module including the EML, a driver amplifier, and bias tee was characterized under the conditions of an operating temperature of 25degC, the modulator bias of 1.4 V, and the DFB laser current of 40 mA. S11 of below -10 dB was obtained for up to 14 GHz and the measured electrical-to-optical response has 3-dB bandwidth of about 20 GHz. View full abstract»

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  • Development of a Broadband Coplanar Waveguide-to-Microstrip Transition With Vias

    Publication Year: 2008 , Page(s): 861 - 872
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1004 KB) |  | HTML iconHTML  

    A transition from coplanar waveguide (CPW)-to-microstrip with vias is often used in wafer-probe measurements. This paper shows how field and impedance matching are used to develop a wideband transition. This paper demonstrates how the presence and placement of the vias affect the bandwidth and alters the impedance of the transition. The measured results on a transition show that a wideband transition with return loss better than 10 dB and an insertion loss less than 1.5 dB up to 36.64 GHz is obtained. The measurements show excellent agreement with simulation. The work presented in this paper provides a better understanding about a CPW-to-microstrip transition with vias as well as design procedures and principles that can be utilized to facilitate the realization of a broadband CPW-to-microstrip transition with vias. View full abstract»

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  • A Unified Finite-Element Solution From Zero Frequency to Microwave Frequencies for Full-Wave Modeling of Large-Scale Three-Dimensional On-Chip Interconnect Structures

    Publication Year: 2008 , Page(s): 873 - 881
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1239 KB) |  | HTML iconHTML  

    It has been observed that a full-wave finite-element-based solution breaks down at low frequencies. This hinders its application to on-chip problems in which broadband modeling from direct current to microwave frequencies is required. Although a static formulation and a full-wave formulation can be stitched together to solve this problem, it is cumbersome to implement both static and full-wave solvers and make transitions between these two when necessary. In this work, a unified finite-element solution from zero frequency to microwave frequencies is developed for full-wave modeling of large-scale three-dimensional on-chip interconnect structures. In this solution, a single full-wave formulation is used. No switching to a static formulation is needed at low frequencies. This is achieved by first identifying the reason why a full-wave eigenvalue-based solution breaks down at low frequencies, and then developing an approach to eliminate the reason. The low frequency breakdown problem was found to be attributed to the discrepant frequency dependence of the real part and the imaginary part of the eigenvalues, which leads to an ill-conditioned eigenvalue system at low frequencies. The discrepant frequency dependence of the real part and the imaginary part is further attributed to the different scaling of the transverse and longitudinal fields with respect to frequency in a transmission-line type structure. By extracting transverse and longitudinal fields separately in the framework of a full-wave formulation, we avoid the numerical difficulty of solving an ill-conditioned eigen-system at low frequencies. The validity of the proposed approach is demonstrated by numerical and experimental results. View full abstract»

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Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering