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Electron Devices, IEEE Transactions on

Issue 2 • Date Feb. 1993

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Displaying Results 1 - 25 of 35
  • Reduction of 1/f noise in multiplexed linear In/sub 0.53/Ga/sub 0.47/As detector arrays via epitaxial doping

    Page(s): 303 - 308
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    A significant (2-5*) reduction in 1/f noise was observed in In0.53Ga0.47 As photodetector arrays read out by a PMOS multiplexer, when the epitaxial InP cap layer doping was changed from undoped to sulfur-doped n type of about 3*1016 cm-3. A further decrease was observed when the InP buffer layer was also changed from undoped to sulfur-doped n type of about 5*1017 cm-3. Data was presented for the variation of 1/f noise, within a temperature range of 18 degrees C to -40 degrees C. Surface states at the InP cap/SiN interface appears to be the primary source of 1/f noise, with the bulk states at the n- In0.53Ga0.47As buffer hetero-interface as a secondary source. Increased n-type doping in the high-bandgap InP cap and buffer layers may reduce electron trapping, and thus 1/f noise. The measured noise spectrum of InGaAs photodetectors varies as fy with y being approximately -0.45 for device structures with doped and undoped InP can layers. For a doped InP buffer layer, this value of y is -0.3. View full abstract»

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  • A comparison of cleaning procedures for removing potassium from wafers exposed to KOH

    Page(s): 292 - 295
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    Silicon, oxidized silicon, and silicon nitride on silicon wafers were exposed to KOH etchant. Three cleaning procedures were used and the remaining surface potassium measured by C-V and SIMS techniques. Bare silicon appears to be the most difficult to clean, followed by oxide, and then nitride. The cleaning procedures appear to be equally effective View full abstract»

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  • A quarter-micrometer interconnection technology using a TiN/Al-Si-Cu/TiN/Al-Si-Cu/TiN/Ti multilayer structure

    Page(s): 296 - 302
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    An interconnection structure using a TiN/Al-1% Si-0.5% Cu/TiN/Al-1% Si-0.5% Cu/TiN/Ti multilayer conductor was investigated as a quarter-micrometer interconnection candidate for 256-Mb DRAMs. It was found that intermetallic compounds such as TiAlx were formed at both grain boundaries of Al-Si-Cu and interfaces between Al-Si-Cu and TiN of the multilayer, resulting in both increase in Vickers hardness and suppression of stress relaxation. The multilayer conductor strip, which was covered with plasma-enhanced chemical vapor deposition silicon nitride (P-SiN), suppressed stress-induced voiding after heat treatment at 500°C. Electromigration tests for quarter-micrometer wide multilayer strips indicated the improvement in the mean time to failure and the increase of the standard deviation View full abstract»

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  • An a-Si:H photoconductive sensor with a gate electrode

    Page(s): 342 - 347
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    A hydrogenated amorphous silicon photoconductive sensor with a gate electrode is developed for a matrix-driven linear image sensor array. The photoresponse time for this new sensor is about 1/3 of that for a conventional photoconductive sensor. A new dynamic model is proposed to analyze the photoresponse characteristics for this sensor. The minimum photoresponse time predicted by the calculation is about 2 ms. This value is markedly short compared with that for a conventional photoconductive sensor (about 5 ms) View full abstract»

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  • Hydrodynamic and Monte Carlo simulation of an electron shock wave in a 1-μm n+-n-n+ diode

    Page(s): 455 - 457
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    Hydrodynamic model simulations of a steady-state electron shock wave in a 1-μm Si semiconductor device at 77 K are compared with a Monte Carlo simulation of the Boltzmann equation using the DAMOCLES program. Excellent agreement between the two different methods for simulating the electron shock wave can be obtained by adjusting the amount of heat conduction in the hydrodynamic model View full abstract»

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  • Anisotype-gate self-aligned p-channel heterostructure field-effect transistors

    Page(s): 278 - 284
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    A new self-aligned p-channel HFET structure was evaluated for application to complementary HFET circuits. The AlGaAs/InGaAs HFET structure uses an anisotype graded n+ InGaAs/GaAs semiconductor gate to enhance the barrier height of the FET, resulting in a significant reduction in gate leakage current at low voltages. With AlGaAs composition of x=0.3, and a thin AlAs spacer of 60 Å, leakage current was reduced by a factor of about 1000 at gate voltage of 1 V, when compared to AlGaAs/InGaAs HIGFET of aluminum content x=0.75. The anisotype PFET maintains high device transconductance, typically 50 mS/mm for 1.3×10 μm PFETs, high reverse breakdown voltages 9-10 V, and low capacitance. Microwave S -parameter characterization resulted in Ft of 5 GHz for a 1×50 μm PFET View full abstract»

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  • High-frequency characteristics of low-temperature pseudo-heterojunction bipolar transistors

    Page(s): 378 - 384
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    The high-frequency characteristics of a pseudojunction bipolar transistor (pseudo-HBT), which operates like an HBT despite a metallurgical homojunction utilizing a bandgap narrowing effect, are analyzed both theoretically and experimentally. Several design features used to achieve a high cutoff frequency at low temperatures are discussed. They include (1) a low-impurity-concentration graft base, (2) an abrupt base profile to obtain a large effective-bandgap difference between the base and the emitter, and (3) an inversely graded base profile, in which the impurity concentration increases from the emitter side to the collector side, to effectively reduce the base transit time. The pseudo-HBT with a low-concentration graft base shows a higher cutoff frequency below 100 K than at room temperature. These features are also appropriate for conventional bipolar transistors operating at low temperatures View full abstract»

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  • Aging analysis of nMOS of a 1.3-μm partially depleted SIMOX SOI technology comparison with a 1.3-μm bulk technology

    Page(s): 364 - 370
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    Hot carrier degradation of nMOS of a 1.3-μm partially depleted rad-hard SOI CMOS technology is analyzed in detail. The relative importances of the maximum electric field, the localization of the trapped charges, and the LDD structure are pointed out through two-dimensional simulations and systematic comparisons with a 1.3-μm CMOS bulk technology. It is shown that the higher degradation rate of the SOI technology logically results from the contradictory constraints between rad-hardness (low-temperature process) and hot carrier resistance requirements. An annealing scheme comparable to the bulk one would lead to similar degradations View full abstract»

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  • Current-drive enhancement limited by carrier velocity saturation in deep-submicrometer fully depleted SOI MOSFETs

    Page(s): 457 - 459
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    Simulations and measurements of SOI MOSFETs are presented with analytical insight to reveal the severe limitation of current-drive enhancement caused by carrier velocity saturation in the deep-submicrometer fully depleted device. For L=0.1 μm, the enhancement, which tends to result from the suppressed body charge and electric field in the thin-film device, is virtually negated by the velocity saturation driven by the high longitudinal electric field View full abstract»

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  • Silicon carbide UV photodiodes

    Page(s): 325 - 333
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    SiC photodiodes were fabricated using 6 H single-crystal wafers. These devices have excellent UV responsivity characteristics and very low dark current even at elevated temperatures. The reproducibility is excellent and the characteristics agree with theoretical calculations for different device designs. The advantages of these diodes are that they will operate at high temperatures and are responsive between 200 and 400 nm and not responsive to longer wavelengths because of the wide 3-eV bandgap. The responsivity at 270 nm is between 70% and 85%. Dark-current levels have been measured as a function of temperature that are orders of magnitude below those previously reported. Thus, these diodes can be expected to have excellent performance characteristics for detection of low light level UV even at elevated temperatures View full abstract»

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  • Modeling temperature effects in the DC I-V characteristics of GaAs MESFET's

    Page(s): 273 - 277
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    A simple model is presented to account for the main temperature effects influencing the DC performance of GaAs MESFETs. The model is based on a consistent solution of heat flow and current equations that accounts for nonuniform power dissipation within the device. The simulation results are satisfactorily compared with experimental data obtained with pulsed and DC measurements performed on conventional devices as well as on suitable test structures View full abstract»

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  • Modeling and experimental results for C(V) in an abrupt isotype n Al0.5Ga0.5As/GaAs heterojunction

    Page(s): 353 - 357
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    The differential capacitance C of an abrupt isotype n Al0.5 Ga0.5As/GaAs heterojunction has been modeled by directly calculating the dependence of the space charge on the voltage V at its terminals. The electron charge distribution was calculated considering the 2-D electron gas by simultaneously solving the Schrodinger and the Poisson equations, DX centers included. Results from this model predict an asymmetric bell-shape dependence of C on V, with a maximum near the contact potential, and are in good agreement with experiment. This further provides experimental evidence of Γ-Γ and X-X valley coupling for electrons traveling across the heterojunction. For voltage values not too close to the contact potential, it was possible to find a simple method, based on a total depletion, that gives a good fit to experiment View full abstract»

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  • Modeling of quantum effects in ultrasmall HEMT devices

    Page(s): 421 - 427
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    Numerical simulation of ultra-submicrometer high electron mobility transistors based upon a set of quantum moment equations is presented. These provide a first quantum description, based upon the moments of the Wigner distribution function. In HEMTs, the conduction electrons are confined in a narrow conduction channel and the short gate lengths (and small aspect ratio) create different potential barriers across the conduction channel than in a long-channel situation. In these small structures, quantum effects are expected to be prominent. A substantial change in the electron density distribution is found to occur due to the inclusion of these quantum corrections, and the total current in the simulated devices is increased by as much as 10% for a 240-nm gate-length device View full abstract»

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  • Properties of nitrogen-implanted SOI substrates

    Page(s): 385 - 391
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    Properties of nitrogen-implanted silicon-on-insulator (SOI) substrates prepared by implanting different doses of 200 keV nitrogen into 50-70 Ω-cm, p-type silicon substrates at a temperature of 500°C were studied. The distribution of nitrogen was studied using Auger electron spectroscopy. The electrical properties of the active overlayer were studied using Hall-effect measurements and capacitance-voltage depth profile analysis. The insulating integrity of the buried nitride was studied by directly measuring the leakage current from top to bottom through the substrate. Additionally, electric field strength and surface roughness measurements were performed. Nitrogen concentrations in the buried layer increased from below to above the stoichiometric value for Si3N4 for increasing dose in the range studied. Nitrogen-related n-type doping is observed in all samples examined, and the magnitude of the doping increased with the increasing implant dose. Insulating buried nitride layers are formed only in samples implanted with very high doses View full abstract»

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  • Infrared imaging using uncooled focal plane arrays of unreticulated 10-μm potassium tantalum niobate films

    Page(s): 320 - 324
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    Potassium tantalum niobate (KTN) films, 10-μm thick, with a nominal Curie temperature of -20°C were formed on polished platinum-coated sacrificial yttria substrates by metalorganic deposition (MOD). These KTN films were used to fabricate focal plane arrays consisting of 128×128 pixels with each pixel on 50-μm centers and 50-μm2. Using f/1 optics and a 2.5-V/μm 2 detector bias, a noise equivalent temperature (NEΔT) of 0.65°C was obtained for the best 1% of the pixels when the detector and blackbody source operated at 25°C View full abstract»

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  • X-ray imaging camera tube using sputter-deposited CdTe/CdS heterojunction

    Page(s): 315 - 319
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    CdTe heterojunction devices have been fabricated for the first time by an RF sputter deposition method for application to X-ray imaging sensors. The electrical resistivities of sputter-deposited polycrystalline CdS and CdTe films are greater than 106 Ω-cm and 109 Ω-cm, respectively. The fabricated CdS/CdTe heterojunction sensor shows a good diode characteristic and a high sensitivity to X-ray radiation. An X-ray imaging camera tube consisting of CdS/CdTe heterojunction photoconductive target shows three times larger responsivity to X-rays than the conventional PbO X-ray tube. The dark current density of the device is observed to be lower than 10 nA/cm2 at 20 V target voltage at room temperature View full abstract»

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  • Light-emitting transistor based on real-space transfer: electrical and optical properties

    Page(s): 250 - 258
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    The charge injection transistor is implemented in InGaAs/InAlAs/InGaAs heterostructure material, grown by molecular beam epitaxy. A complementary collector of p-type conductivity is used for the first time. The real-space transfer of hot electrons leads to a luminescence signal proportional to the injection current. The radiative efficiency is significantly enhanced by a double-heterostructure design of the collector active region, which confines the injected minority carriers. The internal quantum efficiency of the light-emitting transistor is comparable to that of light-emitting diodes. Due to peculiar symmetry of real-space transfer, the optical output signal follows an exclusive-OR function of input voltages. Functional logic operation of the device is demonstrated at room temperature View full abstract»

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  • Nondestructive readout mode static induction transistor (SIT) photo sensors

    Page(s): 334 - 341
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    The nondestructive readout (NDRO) performance of two static induction transistor (SIT) photosensors, a 40×40 pixel area array and a 140-b linear array, is examined. NDRO operation in the SIT sensors is demonstrated by imaging with the area array and by examining the output waveform of the linear array. The charge lost per NDRO cycle in the linear array was 0.014% near the saturation signal level, and no charge loss could be detected at the ⩽0.5 saturation level. NDRO performance in the area array was degraded compared to the linear array, due to the larger value of the load capacitance connected to the output electrode of the SIT. NDRO operation also enables the cancellation of both the photosite reset noise and the signal nonuniformity by subtracting the first NDRO output from the following NDRO outputs, as well as the advantage of monitoring the signal state during the integration period View full abstract»

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  • Scaling properties and short-channel effects in submicrometer AlGaAs/GaAs MODFET's: A Monte Carlo study

    Page(s): 234 - 249
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    Scaling properties of n+-AlxGa1-xAs/GaAs MODFETs with submicrometer gate lengths (LG=0.50 to 0.05 μm) are examined, using Monte Carlo methods. High-frequency performance of MODFETs can be improved by scaling the gate lengths, but various studies suggest that there exists a lower limit for the gate after which no improvement should be expected. The lower limit is determined here to be ≈0.10 μm. Devices with smaller gate lengths than 0.1 μm exhibit degraded transconductance (gm), large shift in threshold voltage due to poor charge control in the channel, and a sharp reduction in output resistance (Ro). It is shown that the drain current saturation in MODFETs is not caused by the velocity saturation effect, but by channel pitch-off. Electron velocities calculated from Monte Carlo simulations and extracted from gm and ft measurements are reconciled View full abstract»

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  • Experimental characterization of the diode-type polysilicon loads for CMOS SRAM

    Page(s): 358 - 363
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    Experimental characterization of the diode-type n+-p-n + poly-Si loads for SRAM applications demonstrates that the resistance of the structure and its response to the bit-line voltages are dominated by such properties of the parasitic thin-film transistor associated with this device as fixed positive charge and `gate' oxide thickness. Topographical effects observed in this study are interpreted in terms of the thickness variation of a dielectric overlaying the poly-Si feature and the fixed positive charges present in this dielectric in the vicinity of the poly-Si surface View full abstract»

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  • Experimental realization of a new transistor

    Page(s): 267 - 272
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    The authors report on the fabrication and characteristics of a unipolar, three-terminal, resonant-tunneling transistor. The operating principle of this new transistor is based on the fact that the quantum mechanical resonant-tunneling probability of hot electrons between the emitter and the collector is switched almost completely on and off, when either the base or the collector bias is swept. The emitter injects hot electrons to the second lowest subband of a thin (100 Å in this work) GaAs quantum well. Subsequently, the hot electrons will either resonantly tunnel to the collector, or relax to the lowest subband and contribute to the base current. As a result of resonant transmission, at 77 K the current-voltage characteristics of the transistor display negative differential resistance with extremely large (4691) peak-to-valley ratio. Furthermore, when biased near resonance, a maximum DC current gain of ~1.2 and a maximum AC current gain of ~11.9 were observed. The first use of a new `tunneling-in and tunneling-out' scheme in contacting a thin quantum well is also demonstrated View full abstract»

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  • A GaAs Schottky-barrier photodiode with high quantum efficiency-bandwidth product using a multilayer reflector

    Page(s): 348 - 352
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    A GaAs Schottky-barrier with high quantum efficiency-bandwidth product has been developed by using a GaAs/Al0.25Ga0.75 As multilayer reflector. The multilayer reflector structure wa designed by using the scattering matrix method. By growing four pairs of Al0.25Ga0.75As (825 Å)/GaAs (330 Å) multilayer reflectors between the undoped GaAs active layer and the buffer layer, a responsivity of 0.6 A/W at λ=0.84 μm was obtained for this device. This represents a 30% improvement over the device without a multilayer reflector. The response speed of the photodiode was measured by the impulse response method, and the results yielded a rise time of 38.45 ps, corresponding to a bandwidth of 9 GHz for this detector View full abstract»

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  • Surface passivation of backside-illuminated indium antimonide focal plane array

    Page(s): 309 - 314
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    A novel surface passivation tailored to a two-dimensional array of small-area, gate-controlled InSb photovoltaic diodes fabricated on etch-thinned bulk InSb wafers, with backside illumination, is presented. The surface passivation is based on a controlled surface treatment that reduces the native oxide and is followed by photon-assisted deposition of SiOx. Thinned bulk n-type InSb with (111) orientation forms two distinctive types of interface on the In and Sb faces, respectively. The In face forms an accumulated interface with reduced surface recombination velocity. The Sb face forms a slightly accumulated interface, with a relatively small concentration of fast and slow surface states. The current-voltage and differential resistance-voltage characteristics of implanted p+-n photodiodes exhibit nearly flat behavior up to 1-V reverse bias with reduced leakage currents. The Ro×A product of small-geometry diodes is 5×104 Ω-cm2 at 77 K View full abstract»

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  • Design and analysis of a new conductivity-modulated power MOSFET

    Page(s): 428 - 438
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    A MOSFET has been developed to offer a performance tradeoff between the ON-resistance, or the forward conduction capability, and the gate turn-on/turn-off switching speed. This conductivity-modulated power DMOS structure (CMDMOS) features a minority-carrier injector adjacent to the current path which allows electrical control of the switching speed/ON-resistance tradeoff. This paper presents an analytical model for the ON-resistance of the device. In this model, the injector hole concentration and the extent of conductivity modulation in the drift region are obtained as functions of the injector current, the drain current, and the device geometry. This work leads to a better understanding of the effect of conductivity modulation, and results in a new power device which provides substantial flexibility in trading off ON-resistance and switching speed View full abstract»

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  • A novel trench planarization technique using polysilicon refill, polysilicon oxidation, and oxide etchback

    Page(s): 459 - 463
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    Planarization of polysilicon trench refill by the method of sequential oxidation and oxide etchback is reported. It is shown to result in an excellent wafer surface topography and improved wafer yield compared to the conventional planarization process that utilizes a blanket reactive ion etch removal of the refill. Trench capacitors with varying aspect ratios were fabricated and tested for gate yield, MOS interface characteristics, and gate oxide reliability. The measured MOS interface properties were excellent for trench capacitors planarized using the technique. The wafer yield was in excess of 90%, as compared to less than 65% for the conventional process. The uniformity of the planarization process across 4-in-diameter silicon wafers was also significantly improved. These results demonstrate that the process is attractive for fabricating high-density trench MOS structures in a manufacturing environment View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology