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Semiconductor Manufacturing, IEEE Transactions on

Issue 4 • Date Nov. 2008

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Displaying Results 1 - 25 of 26
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Page(s): C2
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  • Special Section on the IEEE International Conference on Microelectronic Test Structures

    Page(s): 493 - 494
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  • Extraction of Sheet Resistance and Line Width From All-Copper ECD Test Structures Fabricated From Silicon Preforms

    Page(s): 495 - 503
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1422 KB) |  | HTML iconHTML  

    Test structures have been fabricated to allow electrical critical dimensions (ECD) to be extracted from copper features with dimensions comparable to those replicated in integrated circuit (IC) interconnect systems. The implementation of these structures is such that no conductive barrier metal has been used. The advantage of this approach is that the electrical measurements provide a nondestructive and efficient method for determining critical dimension (CD) values and for enabling fundamental studies of electron transport in narrow copper features unaffected by the complications of barrier metal films. This paper reports on the results of tests which have been conducted to evaluate various extraction methods for sheet resistance and line width values from the current design. View full abstract»

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  • Automatic Extraction Methodology for Accurate Measurements of Effective Channel Length on 65-nm MOSFET Technology and Below

    Page(s): 504 - 512
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (843 KB) |  | HTML iconHTML  

    The length of MOSFET channels is an important circuit design parameter, and this paper focuses on a new industrially-compatible technique using gate-to-channel measurements Cgc(Vg) to provide accurate extraction of the channel length. Thanks to fully-automatic probers, the technique provides large scale extractions and so, statistical-based results can be extracted with a maximized reliability. An in-depth study of parasitic capacitances has been performed to improve the extraction accuracy to within a few nanometers. View full abstract»

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  • Study of CMOS Process Variation by Multiplexing Analog Characteristics

    Page(s): 513 - 525
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1491 KB) |  | HTML iconHTML  

    Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. In this paper we address this need by contributing a test circuit methodology for the extraction of spatial, layout and size dependent variations at both device and interconnect levels. The test chip uses a scan chain approach combined with low-leakage and low-variation switches, and Kelvin sensing connections, providing access to detailed analog device characteristics in large arrays of test devices. Variation measurement using the designed test chip has proven successful for both device and interconnect test structures. The parameter extraction and variation analyses made possible by the variation test chip enable the identification of likely variation sources, quantification of circuit impact and sensitivity, and specification of layout practices for variation minimization. View full abstract»

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  • Fast Characterization of Threshold Voltage Fluctuation in MOS Devices

    Page(s): 526 - 533
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1141 KB) |  | HTML iconHTML  

    Random microscopic fluctuations in the number and location of dopant atoms can cause a large variation in the threshold voltage (VT) of a MOS device. In this paper, we present a technique for fast characterization of random threshold voltage mismatch in MOS devices. Our VT scatter characterization method measures threshold voltage shift by monitoring the change in gate-to-source voltage VGS for a fixed drain current IDS and drain-to-source voltage VDS . We present circuit schematics to characterize VT scatter by measuring VGS variation for a large set of devices arranged in an individually addressable array. We report experimental results of VT scatter measurement from test chips fabricated in 65-nm silicon-on-insulator and 65-nm bulk CMOS processes. We also measure and report the magnitude of local device current mismatch caused by VT fluctuation. View full abstract»

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  • Analysis of Read Current and Write Trip Voltage Variability From a 1-MB SRAM Test Structure

    Page(s): 534 - 541
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1616 KB) |  | HTML iconHTML  

    We present an area efficient test structure that allows measurement of the statistical distribution of SRAM cell read currents and write trip voltages for 1 million SRAM core cells. The data taken from measurements of wafers fabricated with a 90-nm and 65-nm CMOS process flow show that the device variations are Gaussian distributed for more than 1 million devices, covering more than 5 sigma of variation. The analysis of the measured SRAM performances validate Monte Carlo simulations. View full abstract»

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  • Application and Improvement of Precise Resistance Tracing Technique for a Toggle Mode MRAM Evaluation

    Page(s): 542 - 548
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB) |  | HTML iconHTML  

    A precise evaluation technique was created for developing magnetoresistive random access memory (MRAM), especially memory that operates in a toggle-writing mode. This technique enables us to observe the detailed resistance transition of magnetic tunneling junction (MTJ) cells during complicated write operations. It was used to analyze incomplete operation and failed cells, and revealed that the MTJ characteristics in the third quadrant are significantly related to disturb robustness in megabit MRAM. To improve sensitivity to failed cells, we prepared 16-kbit MRAM test structures with a high-speed failed-cell check mode. We found our technique to be a powerful method of failure analysis and expect it to accelerate MRAM development. View full abstract»

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  • Dielectric Relaxation of MIM Capacitor and Its Effect on Sigma-Delta A/D Converters

    Page(s): 549 - 564
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1873 KB) |  | HTML iconHTML  

    Dielectric relaxation of capacitors is one of the error sources when determining the accuracy of analog sampled-data systems that are based on charge storage. To perform an accurate characterization of the dielectric relaxation of metal-insulator-metal (MIM) capacitor, techniques based on the voltage recovery principle and the Curie Von Schweidler discharge current approach are developed. To model the dielectric relaxation of the MIM capacitor, Dow's model is selected. An algorithm for the model parameter extraction on the Curie Von Schweidler current has been developed, which shows the phenomenon of dielectric relaxation in detail and is very fast to determine the parameters. Based on the measurement data, a set of model parameters is extracted and verified, which approximates the Curie Von Schweidler law over a sufficiently wide interval of time constants. To study the effect of the dielectric relaxation on the circuit performance of high resolution sigma-delta ADC, a 12-b incremental ADC has been selected as an example for simulation. The simulation results show that the effect of the dielectric relaxation on the performance of the 12-b ADC is not significant. We show that the .major reason for this is that the noise shaping which is enforced by the integrators in SigmaDelta-ADC is almost not affected by the dielectric relaxation phenomenon. View full abstract»

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  • Special Section on the International Symposium on Semiconductor Manufacturing 2007 (ISSM 2007)

    Page(s): 565 - 566
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  • A Fast QC Method for Testing Contact Hole Roughness by Defect Review SEM Image Analysis

    Page(s): 567 - 572
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1726 KB) |  | HTML iconHTML  

    We propose a new and fast method for monitoring contact hole roughness (CHR), which can be a major yield-loss factor for advanced SRAMs. The method, defect-review scanning electron microscopy (SEM) image processing, can monitor CHR 100 times faster than the conventional method by critical dimension (CD)-SEM. The speed can facilitate faster identification of process countermeasures by, for example, making detailed monitoring of CHR variation within a wafer practicable. Results for CHR obtained by both new and conventional methods show similar trends for differences in process conditions. Also, we experimentally confirmed the new method's measuring variation of the rate of deformed contact holes. View full abstract»

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  • Controlling Ambient Gas in Slot-to-Slot Space Inside FOUP to Suppress Cu-Loss After Dual Damascene Patterning

    Page(s): 573 - 577
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1282 KB) |  | HTML iconHTML  

    We investigated a Cu-loss problem after dual-damascene patterning during manufacturing; that is, more than a dozen wafers were stored in a FOUP. We found that a decreased yield due to the Cu-loss strongly depended on the wafer position in a FOUP and on the queue time between etching and wet cleaning. We developed a Cu-oxidation model to explain what happens in a FOUP during the queue time; that is, the F content, which catalyze Cu-oxidation, in the post-etch residue gradually evaporate into the slot-to-slot space. The ambient gas analysis in a FOUP showed that F-containing gas evaporates from the post-etch wafers, and that the evaporation is gradual, which is consistent with our model. On the basis of our model, we controlled ambient gas in the slot-to-slot space. The increased yield showed that the Cu-loss problem was successfully suppressed. View full abstract»

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  • Advanced Method for Monitoring Copper Interconnect Process

    Page(s): 578 - 584
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1068 KB) |  | HTML iconHTML  

    Stabilizing the copper interconnect process is the key to improving yield and reliability. A stable process for forming adequate grains in a copper film is important, but there is no proper method for monitoring the grains in that film. We introduce the micro-haze method, an advanced method for monitoring grain size using scattering light. We experimentally verified the effectiveness of the method and concluded that the method enables the monitoring the grains in a copper film. View full abstract»

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  • A Novel Wafer-Yield PDF Model and Verification With 90–180-nm SOC Chips

    Page(s): 585 - 591
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1028 KB) |  | HTML iconHTML  

    In this paper, we describe a new wafer-yield distribution model, which agrees well with experiment using fabricated products with various process technologies. To investigate physical reasoning of the proposed model, we firstly measure effective defect density of chips regarding to spatial dependency in a wafer. It is clarified that the defect density near wafer edge is a couple of times larger than that at the rest of wafer area. Note that the increase of defect at wafer edge causes a significant yield loss in production process lines. View full abstract»

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  • 300-mm Prime Gaps That Need to Be Addressed to Boost Productivity

    Page(s): 592 - 599
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (454 KB) |  | HTML iconHTML  

    This paper analyzes 300-mm manufacturing inefficiencies that need to be addressed to improve productivity in the next-generation factory, classifies them into seven general themes, quantifies their business impacts, and identifies specific improvements needed for each as the basis for collaboration between integrated device manufacturers and equipment vendors to address the issues. View full abstract»

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  • Levels of Capacity and Material Handling System Modeling for Factory Integration Decision Making in Semiconductor Wafer Fabs

    Page(s): 600 - 613
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1006 KB) |  | HTML iconHTML  

    As the costs of building a new wafer fab increase, a detailed simulation model representing the production operations, the tools, the automated material handling systems (AMHS), and the tool-AMHS interactions is needed for accurately planning the capacity of these facilities. The problem is that it currently takes too long to build, experiment, and analyze a sufficiently detailed model of a fab. The key for building accurate and computationally efficient fab models is to decide on the right amount of model details, specifically those details representing the equipment capacity and the AMHS. This paper identifies a method for classifying a fab model by the level of capacity detail, the level of AMHS detail, or the level of capacity/AMHS detail. Within the capacity/ AMHS modeling level, our method further differentiates between detailed integrated capacity/AMHS models and abstract coupled capacity/AMHS models. The proposed classification method serves as the basis of a framework that helps users select the system components to be modeled within a desired level of detail. This research also provides a review of past-published literature summarizing the work done at each of the proposed fab modeling levels. A case study comparing the performance between an integrated capacity/AMHS model and a coupled capacity/AMHS model is presented. The study demonstrates that the coupled model generates cycle time estimates that are not statistically different than those generated by the integrated model. This paper also shows that the coupled model can improve CPU time by approximately 98% in relation to the integrated model. View full abstract»

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  • Modeling and Forecasting of Defect-Limited Yield in Semiconductor Manufacturing

    Page(s): 614 - 624
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (475 KB) |  | HTML iconHTML  

    A detailed cause-and-effect stochastic model is developed to relate the type, size, location, and frequency of observed defects to the final yield in IC manufacturing. The model is estimated on real data sets with a large portion of unclassified defects and un inspected layers, and in presence of clustering of defects. Results of this analysis are used for evaluating kill ratios and effects of different factors, identifying the most dangerous cases and the most probable causes of failures, forecasting the yield, and designing optimal yield-enhancement strategies. View full abstract»

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  • Automatic Identification of Defect Patterns in Semiconductor Wafer Maps Using Spatial Correlogram and Dynamic Time Warping

    Page(s): 625 - 637
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2136 KB) |  | HTML iconHTML  

    A wafer map is a graphical illustration of the locations of defective chips on a wafer. Defective chips are likely to exhibit a spatial dependence across the wafer map, which contains useful information on the process of integrated circuit (IC) fabrication. An analysis of wafer map data helps to better understand ongoing process problems. This paper proposes a new methodology in which spatial correlogram is used for the detection of the presence of spatial autocorrelations and for the classification of defect patterns on the wafer map. After the detection of spatial autocorrelation based on our proposed spatial randomness test using spatial correlogram, the dynamic time warping algorithm which provides nonlinear alignments between two sequences to find optimal warping path is adopted for the automatic classification of spatial patterns based on spatial correlogram. We also develop generalized join-count (JC)-based statistics and then propose a procedure to determine the optimal weights of JC-based statistics. The proposed method is illustrated using real-life examples and simulated data sets. The experimental results show that our method is robust to random noise and has a robust performance regardless of defect location and size. View full abstract»

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  • Fast Lithography Image Simulation By Exploiting Symmetries in Lithography Systems

    Page(s): 638 - 645
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1047 KB) |  | HTML iconHTML  

    Lithography simulation has been widely used in many applications, such as optical proximity correction, in the semiconductor industry. It is important to reduce the runtime of such simulations. Dedicated hardware and parallel computation have been used to reduce the runtime. For full chip simulation, the simulation method, optimal coherent approximations (OCAs), is widely used. But, it has not been improved since its first inception. In this paper, we improve it by considering the symmetric properties of lithography systems. The new method could speed up the runtime by 2times without loss of accuracy. We demonstrate the speedup is applicable to vectorial imaging model as well. In case the symmetric properties do not hold strictly, the new method can be generalized such that it could still be faster than the old method. View full abstract»

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  • Novel Carbon-Cage-Based Ultralow- k Materials: Modeling and First Experiments

    Page(s): 646 - 660
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    A new class of materials is presented that is supposed to be a potential candidate for isolating ultra low-k thin films between metal on-chip interconnects in future CMOS technology nodes. The ideal structure of the novel carbon-cage-based materials is described by a model that assumes an ordered network (mosaic structure) with fullerenes (C60) as the nodes and linker molecules along the edges of the mosaic cells. The interior of the network represents a nanopore of a 1-nm scale. According to the molecular design-based model, structures with simple cubic and diamond-like topology of the network are considered promising candidates. A dielectric constant (k value) of 1.7 and an elastic bulk modulus of about 20 GPa are predicted of ideal combinations of network topology and linker molecules. First experimental results, based on electron energy loss spectroscopy, X-ray absorption spectroscopy, nanoindentation, and atomic force microscopy are presented. A more controlled film fabrication process is needed to get more homogeneous thin films with characteristic material parameters as predicted by the model. View full abstract»

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  • An Analytical Model to Describe the Efficiency of an Immersion Rinsing Process

    Page(s): 661 - 667
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (315 KB) |  | HTML iconHTML  

    In this paper, a simple model is presented, describing an immersion rinsing process for flat solid substrates (e.g., semiconductor wafers). It is assumed that together with the solid a layer of processing liquid is transferred into a tank filled with rinsing liquid. The model calculates the replacement of the processing liquid with rinsing liquid as a function of the rinse time and the position in the tank. For static rinsing systems an analytical expression is readily obtained. For dynamic systems (where liquid convection plays a role) the concept of a convective boundary layer is introduced. It is assumed that within this boundary layer diffusion is the dominant transport mechanism while outside the boundary layer convection is dominant. Under these assumptions an analytical expression can also be obtained for dynamic rinsing with the thickness of the convective boundary layer as a process parameter. The resulting analytical expressions can be readily used to calculate the concentration of remaining processing liquid in the vicinity of the solid substrate as a function of rinse time. This provides a good way to determine the efficiency of the rinsing process. Moreover, these expressions allow us to assess the effect of changes in boundary layer thickness and thus can help with the optimization of existing rinsing processes. View full abstract»

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  • High-Efficiency PFC Abatement System Utilizing Plasma Decomposition and Ca(OH) _{2} /CaO Immobilization

    Page(s): 668 - 675
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (997 KB) |  | HTML iconHTML  

    In order to minimize contributions to global warming, it is important to develop a perfluorocompound (PFC) abatement system that can remove PFCs effectively with low electric power. We have developed a new PFC abatement system consisting mainly of a 2-MHz ICP plasma source and two Ca(OH)2/CaO columns operated under a decompression pressure. Reactive fluorinated compounds including SiF4 are immobilized in the Ca(OH)2/CaO columns without a water scrubber. Stable compounds such as CF4 are excited by the 2-MHz ICP plasma. When the emissions from an Si oxidation film etching process chamber were treated by this abatement system, F2 equivalent removal efficiency was 99.6%, which was about one order of magnitude larger than that of a conventional abatement system. But the CO2 equivalent removal efficiency was calculated to be 91.4% because over 95% of CO2 equivalent emissions were caused by the plasma source power consumption of 2.4 kWh. It means that minimization of the plasma source power consumption, depending on PFC emissions, is a very effective method of minimizing contributions to global warming in a manner similar to improving the PFC removal efficiency. View full abstract»

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  • Technical program - abstract submission

    Page(s): 676
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  • 2008 Index IEEE Transactions on Semiconductor Manufacturing Vol. 21

    Page(s): 677 - 688
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721