By Topic

# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

## Filter Results

Displaying Results 1 - 24 of 24

Publication Year: 2008, Page(s):C1 - C4
| PDF (46 KB)
• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

Publication Year: 2008, Page(s): C2
| PDF (42 KB)
• ### A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based Digital Microfluidic Biochips

Publication Year: 2008, Page(s):1905 - 1917
Cited by:  Papers (29)
| | PDF (1561 KB) | HTML

Digital microfluidic biochips are revolutionizing high-throughput DNA, immunoassays, and clinical diagnostics. As high-throughput bioassays are mapped to digital microfluidic platforms, the need for design automation techniques for pin-constrained biochips is being increasingly felt. However, most prior work on biochips computer-aided design has assumed independent control of the underlying electr... View full abstract»

• ### A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics

Publication Year: 2008, Page(s):1918 - 1927
Cited by:  Papers (8)
| | PDF (943 KB) | HTML

This paper presents the first boundary element method (BEM) impedance extraction algorithm for interconnects with multiple dielectrics. Multiple dielectrics are common in integrated circuits and packages. However, previous BEM algorithms, including FastImp and FastPep, assume uniform dielectric due to their limitation, thus causing considerable errors. Our algorithm introduces a circuit formulatio... View full abstract»

• ### BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips

Publication Year: 2008, Page(s):1928 - 1941
Cited by:  Papers (56)
| | PDF (928 KB) | HTML

Due to recent advances in microfluidics, digital microfluidic biochips are expected to revolutionize laboratory procedures. One critical problem for biochip synthesis is the droplet routing problem. Unlike traditional very large scale integration routing problems, in addition to routing path selection, the biochip routing problem needs to address the issue of scheduling droplets under practical co... View full abstract»

• ### An Implicit Approach to Minimizing Range-Equivalent Circuits

Publication Year: 2008, Page(s):1942 - 1955
Cited by:  Papers (1)
| | PDF (508 KB) | HTML

Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous approaches use the binary decision diagram (BDD) technique to compute the range of one circuit and then reconstruct the circuit using the computed range. Although the size of the new circuit is significantly re... View full abstract»

• ### Skewed Flip-Flop and Mixed-$V_{t}$ Gates for Minimizing Leakage in Sequential Circuits

Publication Year: 2008, Page(s):1956 - 1968
Cited by:  Patents (1)
| | PDF (1564 KB) | HTML

Mixed V t has been widely used to control leakage without affecting circuit performance. However, existing approaches only target combinational circuits, even though sequential elements such as flip-flops contribute an appreciable proportion of the total leakage. Applying high V t to ordinary flip-flops would reduce the number of combinational gates that can be ... View full abstract»

• ### Energy and Performance Optimization of Demand Paging With OneNAND Flash

Publication Year: 2008, Page(s):1969 - 1982
Cited by:  Papers (7)
| | PDF (1474 KB) | HTML

New fusion memory devices consisting of multiple heterogeneous memory components in a single die or package offer efficient ways to optimize embedded systems in terms of energy, performance, and cost. Samsung Electronics recently announced the OneNAND fusion memory, in which a NAND flash array is integrated with dual SRAM buffers to provide a nor-type I/O interface. OneNAND has the low cost and la... View full abstract»

• ### A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations

Publication Year: 2008, Page(s):1983 - 1995
Cited by:  Papers (23)
| | PDF (481 KB) | HTML

The increase of statistical variations in advanced nanometer CMOS technologies poses a major challenge for digital circuit design. In this paper, we study the impact of random variations on the delay variability of a gate and derive simple and scalable statistical models to effectively evaluate delay variations in the presence of within-die variations. The derived models are verified and compared ... View full abstract»

• ### Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method

Publication Year: 2008, Page(s):1996 - 2006
Cited by:  Papers (12)
| | PDF (606 KB) | HTML

This paper proposes a novel stochastic method for analyzing the voltage drop variations of on-chip power grid networks, considering lognormal leakage current variations. The new method, called StoEKS, applies Hermite polynomial chaos to represent the random variables in both power grid networks and input leakage currents. However, different from the existing orthogonal polynomial-based stoc... View full abstract»

• ### Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs

Publication Year: 2008, Page(s):2007 - 2016
Cited by:  Papers (5)
| | PDF (1131 KB) | HTML

Given a set of pins and a set of obstacles on routing layers, a multilayer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) connects these pins by rectilinear edges within layers and vias between layers and avoids running through any obstacle to construct a Steiner tree with a minimal total cost. The ML-OARSMT problem is very important for many very large scale integration designs wi... View full abstract»

• ### MaizeRouter: Engineering an Effective Global Router

Publication Year: 2008, Page(s):2017 - 2026
Cited by:  Papers (24)
| | PDF (1122 KB) | HTML

In this paper, we present the complete design and architectural details of MaizeRouter. MaizeRouter reflects a significant leap in progress over existing publicly available routing tools yet relies upon relatively simple operations, including extreme edge shifting, a technique aimed primarily at the efficient reduction of routing congestion, and edge retraction, ... View full abstract»

• ### Presynthesis Area Estimation of Reconfigurable Streaming Accelerators

Publication Year: 2008, Page(s):2027 - 2038
Cited by:  Papers (1)
| | PDF (885 KB) | HTML

In this paper, we propose algorithms for presynthesis estimation of hardware cost of a streaming accelerator. Our proposed estimation method helps to accelerate the design-space-exploration phase by orders of magnitude by eliminating the need to perform logic and physical synthesis in each iteration. We present algorithms to perform early cost estimation of resources that are specific to a streami... View full abstract»

• ### An Efficient Unknown Blocking Scheme for Low Control Data Volume and High Observability

Publication Year: 2008, Page(s):2039 - 2052
Cited by:  Papers (7)  |  Patents (2)
| | PDF (566 KB) | HTML

This paper presents an efficient method to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and increase the number of scan cells that are observed by temporal compactors. Control patterns, which specify values required at the control signals of the blocking logic, are compressed by linear feedback shift register rese... View full abstract»

• ### Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

Publication Year: 2008, Page(s):2053 - 2067
Cited by:  Papers (3)
| | PDF (1464 KB) | HTML

The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuitry that is defined on the lithography scale. In this paper, we evaluate the addressing scheme of the decoder circuit for NW crossbar arrays, bas... View full abstract»

• ### Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants

Publication Year: 2008, Page(s):2068 - 2082
Cited by:  Papers (19)
| | PDF (868 KB) | HTML

We propose a methodology to formally prove protocol compliance for communication blocks in System-on-Chip (SoC) designs. In this methodology, a set of operational properties is specified with respect to the states of a central finite state machine (FSM). This central FSM is called main FSM and controls the overall behavior of the design. In order to prove a set of compliance properties, we develop... View full abstract»

• ### A Distributed Heuristic Algorithm for the Rectilinear Steiner Minimal Tree Problem

Publication Year: 2008, Page(s):2083 - 2087
Cited by:  Papers (2)
| | PDF (187 KB) | HTML

Rectilinear Steiner minimal tree (RSMT) problem finds a minimum length tree that interconnects a given set of points by only horizontal and vertical line segments and by using extra points if necessary. In this paper, to speedup the RSMT construction, two recently developed successful heuristic algorithms, namely rectilinear steiner tree (RST) by Zhou and batched greedy algorithm (BGA) by Kahng , ... View full abstract»

• ### Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric

Publication Year: 2008, Page(s):2088 - 2092
Cited by:  Papers (14)
| | PDF (215 KB) | HTML

This paper proposes an algorithm that provides both dynamic voltage scaling and power shutdown to minimize the total energy consumption of an application executed on an on-chip multiprocessor. The proposed algorithm provides an extended schedule and stretch method, where task computations are iteratively stretched within the slack of a time-constrained dependent task set. In addition, the break-ev... View full abstract»

• ### Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test

Publication Year: 2008, Page(s):2092 - 2097
Cited by:  Papers (15)
| | PDF (410 KB) | HTML

Scan chain division has been successfully used to control shift power by enabling mutually exclusive flip-flops at different times during the scan cycle. However, to control capture power without losing transition fault coverage during at-speed scan test, the existing automatic test pattern generation (ATPG) flows need to be modified. In this paper, we present a novel scan chain division algorithm... View full abstract»

• ### Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits

Publication Year: 2008, Page(s):2097 - 2101
Cited by:  Papers (18)
| | PDF (625 KB) | HTML

Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices most likely have the similar parameter variation. The key performance of many analog circuits is directly related to accurate capacitance ratios. Parallel unit capacitances have a great effect on reducing... View full abstract»

• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

Publication Year: 2008, Page(s): 2102
| PDF (24 KB)
• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

Publication Year: 2008, Page(s): C3
| PDF (27 KB)

Publication Year: 2008, Page(s): 2103
| PDF (269 KB)
• ### Order form for reprints

Publication Year: 2008, Page(s): 2104
| PDF (353 KB)

## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu