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Design & Test of Computers, IEEE

Issue 5 • Date Sept.-Oct. 2008

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Displaying Results 1 - 25 of 28
  • [Front cover]

    Publication Year: 2008 , Page(s): c1
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  • call-for-papers

    Publication Year: 2008 , Page(s): c2
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  • Special Issue on High-Level Synthesis

    Publication Year: 2008 , Page(s): 393
    Cited by:  Papers (2)
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  • [Advertisement]

    Publication Year: 2008 , Page(s): 394
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  • Interconnect challenges in the multicore era

    Publication Year: 2008 , Page(s): 396
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  • Staff listing

    Publication Year: 2008 , Page(s): 397
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  • ITC 2008 Highlights

    Publication Year: 2008 , Page(s): 398 - 399
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  • Guest Editors' Introduction: Tackling Key Problems in NoCs

    Publication Year: 2008 , Page(s): 400 - 401
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    This special issue highlights recent innovations in network on a chip (NoC) design. The four articles fall into two main thrusts: the first three focus on design methodology challenges in NoCs; the final article demonstrates a practical case study implementation of an NoC. View full abstract»

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  • COSI: A Framework for the Design of Interconnection Networks

    Publication Year: 2008 , Page(s): 402 - 415
    Cited by:  Papers (11)
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    This article presents a software framework for communication infrastructure synthesis of distributed systems, which is critical for overall system performance in communication-based design. Particular emphasis is given to on-chip interconnect synthesis of multicore designs. View full abstract»

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  • A Quality-Driven Design Approach for NoCs

    Publication Year: 2008 , Page(s): 416 - 428
    Cited by:  Papers (2)
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    This article advocates a systematic approach to improve NoC design quality by guiding architectural choices according to the difficulty of verification and test. The authors propose early quality metrics for added test, monitoring, and debug hardware. View full abstract»

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  • [Advertisement]

    Publication Year: 2008 , Page(s): 429
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  • Characterization of Equalized and Repeated Interconnects for NoC Applications

    Publication Year: 2008 , Page(s): 430 - 439
    Cited by:  Papers (9)
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    As the number of cores increases and onand off-chip bandwidth demand rises, it is becoming increasingly more difficult to rely on conventional interconnects and remain within the chip power budget. This article explores leveraging equalization for global and semi-global long interconnects to overcome this problem. View full abstract»

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  • [Advertisement]

    Publication Year: 2008 , Page(s): 440
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  • [Advertisement]

    Publication Year: 2008 , Page(s): 441
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  • An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC

    Publication Year: 2008 , Page(s): 442 - 451
    Cited by:  Papers (4)
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    Data-intensive processing in embedded systems is receiving much attention in multimedia computing and high-speed telecommunications. The memory bandwidth problem of traditional von Neumann architectures, however, is impairing processor efficiency. On the other hand, ASIC designs suffer from skyrocketing manufacturing costs and long development cycles. This results in an increasing need for postfab... View full abstract»

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  • Signal Integrity Enhancement in Digital Circuits

    Publication Year: 2008 , Page(s): 452 - 461
    Cited by:  Papers (4)
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    This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths. This methodology makes digital circuits more robust to power line fluctuations while maintaining the at-spee... View full abstract»

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  • Hardware-Software Approaches to In-Circuit Emulation for Embedded Processors

    Publication Year: 2008 , Page(s): 462 - 477
    Cited by:  Papers (1)
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    In-circuit emulators have become part of the permanent structure of microprocessor cores to support on-chip test and debug activities in highly integrated environments such as SoCs. However, ICE design styles and operation principles are quite diverse. This article presents a taxonomy based on the notions of foreground and background operations and hardwaresoftware implementation alternatives to o... View full abstract»

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  • Verification of Pin-Accurate Port Connections

    Publication Year: 2008 , Page(s): 478 - 486
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    Before verifying the functionality of SoCs, designers must ensure the correctness of the pin-accurate interfaces of up to hundreds of integrated IP blocks. This article presents a new connection model and a corresponding error model for pin-accurate port connections, along with an algorithm for generating the minimum pattern set, a methodology for diagnosing errors, and a port connection verificat... View full abstract»

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  • [Advertisement]

    Publication Year: 2008 , Page(s): 487
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  • Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow

    Publication Year: 2008 , Page(s): 488 - 494
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    In this article, the author provides an assessment of the current status and needs of electronic systems, their design, and their evolution. To put this analysis into perspective and to motivate it, the author considers the progress of electronics over the past 50 years, from the invention of the transistor to the microprocessor, to the design of complex multiprocessors that see today within gamin... View full abstract»

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  • [Advertisement]

    Publication Year: 2008 , Page(s): 495
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  • Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]

    Publication Year: 2008 , Page(s): 496 - 497
    Request Permissions | Click to expandAbstract | PDF file iconPDF (244 KB) |  | HTML iconHTML  

    The focus of this volume is on postsilicon adaption to overcome process and environmental variations, to ensure that a design operates to specifications even in the presence of process and environmental variations. Some of the topics covered include: an introduction, discussing sources of variation and the notion of a control system with a feedback loop to adaptively compensate for variations; ada... View full abstract»

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  • [Advertisement]

    Publication Year: 2008 , Page(s): 498
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  • CEDA Currents

    Publication Year: 2008 , Page(s): 500 - 502
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  • [Advertisement]

    Publication Year: 2008 , Page(s): 503
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty