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IEE Proceedings E - Computers and Digital Techniques

Issue 4 • Date July 1980

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Displaying Results 1 - 14 of 14
  • Special-purpose computer for video signal processing in radar systems

    Publication Year: 1980, Page(s):109 - 119
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1392 KB)

    A special-purpose computer for processing video signals in radar systems is presented. The main part of the computer is an array of Q processing elements (PEs), all driven by the same microprogrammed control block. Each PE handles four bits in parallel, and carries out arithmetic and logic operations on operands from 4¿¿16 bits long. It contains a local memory and an unconventional microprocessor ... View full abstract»

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  • Conference report: 10th international symposium on multiple-valued logic

    Publication Year: 1980
    IEEE is not the copyright holder of this material | PDF file iconPDF (115 KB)
    Freely Available from IEEE
  • Evaluation of some proposed name-space architectures using ISPS

    Publication Year: 1980, Page(s):120 - 125
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (831 KB)

    In name-space architectures, the mapping of names onto fast registers is a hardware, rather than a software, function. The MU5 computer is an example of such an architecture, having a single-address instruction format with some stacking facilities, and this paper introduces proposed two-store-address and three-store-address architectures developed from MU5 concepts. ISPS descriptions of all three ... View full abstract»

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  • Evaluation of computer architecture using ISPS

    Publication Year: 1980, Page(s):126 - 135
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1219 KB)

    The Instruction Set Processor (ISP) notation was originally developed as a means of describing formally the behavioural aspects of computer systems. ISPS is a computer language based on this notation, and for which a compiler and simulator have been produced. An ISPS description of the MU5 computer has been written, verified, and used in a series of evaluation experiments conducted at Carnegie-Mel... View full abstract»

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  • Efficient program for decoding the (255, 223) Reed-Solomon code over GF (28 ) with both errors and erasures, using transform decoding

    Publication Year: 1980, Page(s):136 - 142
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (569 KB)

    To decode a (255, 223) Reed-Solomon code over GF(28), a fast Fourier-like transform over GF(28) has been developed to compute the syndromes and the error-erasure vectors of the transmitted code words. This new simplified transform decoder is implemented in a program on a digital computer. The (255, 223) Reed-Solomon code over GF(28) is being proposed as a NASA standard for concatenation with a (7,... View full abstract»

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  • Fast generation of chain code

    Publication Year: 1980, Page(s):143 - 147
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (385 KB)

    The chain code is an attractive and economical method of coding a binary image, but it is not particularly easy to generate. This article describes a hardware/software mechanism for improving the speed of chain-code generation. At the heart of the procedure is an r.o.m. which is used to detect certain (binary) patterns in the input image. The r.o.m. also controls the acquisition of data by an r.a.... View full abstract»

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  • Hardware realisation of binary search algorithm

    Publication Year: 1980, Page(s):148 - 151
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (532 KB)

    It is shown how, by augumenting a microprocessor or mincomputer with a relatively small amount of iteratively driven logic, the operation of table lookup using a binary search algorithm can be speeded up by 1¿¿ to 2 orders of magnitude. The approach is very suitable for 1.s.i. implementation as a standard peripheral device for a microprocessor. View full abstract»

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  • Infotech State-of-the-Art Report on Supercomputers

    Publication Year: 1980, Page(s):151 - 152
    IEEE is not the copyright holder of this material | PDF file iconPDF (327 KB)
    Freely Available from IEEE
  • Number Theory in Digital Signal Processing

    Publication Year: 1980
    IEEE is not the copyright holder of this material | PDF file iconPDF (175 KB)
    Freely Available from IEEE
  • Systematic Construction of Data Base Applications

    Publication Year: 1980
    IEEE is not the copyright holder of this material | PDF file iconPDF (175 KB)
    Freely Available from IEEE
  • Conference reports: Spring Compcon '80

    Publication Year: 1980, Page(s):153 - 154
    IEEE is not the copyright holder of this material | PDF file iconPDF (317 KB)
    Freely Available from IEEE
  • Conference reports: 7th international symposium on computer architecture

    Publication Year: 1980, Page(s):154 - 155
    IEEE is not the copyright holder of this material | PDF file iconPDF (234 KB)
    Freely Available from IEEE
  • Erratum: Testing for numerical computations

    Publication Year: 1980
    IEEE is not the copyright holder of this material | PDF file iconPDF (73 KB)
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  • Erratum: Sampled multiserver queues with general arrivals and deterministic service time

    Publication Year: 1980
    IEEE is not the copyright holder of this material | PDF file iconPDF (73 KB)
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