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Computers and Digital Techniques, IEE Proceedings E

Issue 6 • Date November 1987

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Displaying Results 1 - 7 of 7
  • Design technique for dynamically evolving N-tuple nets

    Publication Year: 1987 , Page(s): 265 - 269
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (573 KB)  

    N-tuple nets are conceptually a highly parallel architecture. However, high-speed serial emulations of N-tuple nets offer considerable advantages of flexibility and cost efficiency in applications requiring only moderate bandwidth. In the paper a software technique for designing dynamically evolved N-tuple nets is described and the process whereby the designed structure can be progressively mapped... View full abstract»

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  • Radix-4 modules for high-performance bit-serial computation

    Publication Year: 1987 , Page(s): 271 - 276
    Cited by:  Papers (3)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (700 KB)  

    We describe a technique to double the throughput of bit-serial computational networks, while retaining the many advantages associated with this architectural approach. In essence this technique relies on a 2-wire radix-4 representation of serial data: a step towards bit parallelism. As the cost of data storage associated with bit-serial architectures is not increased by this technique, it has a fa... View full abstract»

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  • On the design of easily testable LFSR counters for frequency division

    Publication Year: 1987 , Page(s): 277 - 280
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (409 KB)  

    The paper discusses the design of easily testable counters for use in frequency division circuits. The proposed approach, based on linear feedback shift registers, requires the minimum number of memory elements. The algorithms for counter synthesis and test-pattern generation are described in detail View full abstract»

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  • Orbital architectures with dynamic reconfiguration

    Publication Year: 1987 , Page(s): 281 - 287
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (745 KB)  

    Several broad classes of nonplanar arrays/architectures are analysed. Included in this are architectures which have a natural interpretation in terms of data flow on the surface of a torus, sphere, cylinder and other geometric forms. A definitive quantification is given of the several architectural classes and architectural reconfiguration is demonstrated to facilitate iterative computations. View full abstract»

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  • Bus scheduling for a multiple-processor system with shared buses

    Publication Year: 1987 , Page(s): 288 - 294
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (681 KB)  

    The operation and performance of a multiple-processor system with shared buses is analysed. The model developed is applicable to real-time computations consisting of two pipelined tasks in which the first task is partitioned into a number of independent subtasks on separate processors. These processors transmit their output data to the processor(s) executing the second task over shared buses. When... View full abstract»

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  • Performance evaluation of spanning multiaccess channel hypercube interconnection network

    Publication Year: 1987 , Page(s): 295 - 302
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1039 KB)  

    The spanning multiaccess channel hypercube (SMCH) is a distributed computer interconnection structure, based on a hypercube topology, where processors are connected using multiaccess channels spanning all dimensional axes. The channel access arbitration is achieved through demand assignment multiple access (DAMA) protocols. We compare the SMCH to the generalised hypercube (GHC), the nearest neighb... View full abstract»

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  • Book review: A Practical Introduction to the New Logic Symbols

    Publication Year: 1987
    Save to Project icon | PDF file iconPDF (177 KB)  
    Freely Available from IEEE