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IEE Proceedings E - Computers and Digital Techniques

Issue 4 • Date July 1987

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Displaying Results 1 - 6 of 6
  • Hierarchical multiprocessor architecture

    Publication Year: 1987, Page(s):161 - 167
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (991 KB)

    The paper is concerned with a multiprocessor computer architecture, which offers a flexible and high-performance system at low cost. The processing elements in the design may be connected as a hierarchy, and the system software supports a virtual memory which may be distributed throughout the processing elements. The principal form of communication is therefore through shared data structures. The ... View full abstract»

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  • Analysis of input and output configurations for use in four-valued CCD programmable logic arrays

    Publication Year: 1987, Page(s):168 - 176
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1085 KB)

    As in binary, a multiple-valued programmable logic array (PLA) realises a sum-ofproducts expression specified by the user. However, in multiple-valued logic, there are many more operations than in binary, and an important question is the choice of operations which provides the greatest number of functions for a given chip area. In this paper, we analyse various PLA configurations using operations ... View full abstract»

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  • Vertical migration: an experimental study of the candidate-selection problem

    Publication Year: 1987, Page(s):177 - 188
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1066 KB)

    Vertical migration is a well known technique to improve the performance of a computer system in which the selected primitives (instruction sequences or functions) are moved to a lower level in the software/firmware hierarchy. Concerning the steps to be performed to apply this technique, we have taken into account in the paper the selection problem of vertical-migration candidates. To solve the sel... View full abstract»

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  • New pipelined vector-reduction arithmetic unit for FIR filter implementation

    Publication Year: 1987, Page(s):189 - 196
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (804 KB)

    In realising an N-tap finite impulseresponse (FIR) filter, N multiplications and N ¿¿ 1 additions must be performed during every sampling interval. The multiplication process can be pipelined easily because there is no recurrence. The (N ¿¿ l)-port addition process is essentially a vector-reduction process with inherent recurrence and is a bottleneck of hardware utilisation when implemented using ... View full abstract»

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  • Local rerouting with virtual cut-through switching

    Publication Year: 1987, Page(s):197 - 202
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (789 KB)

    The `virtual cut-through switching¿¿ method of message transmission in computer communication is modified to achieve further reduction of message transmission delays. A local rerouting feature is also added, so that this `modified cut-through switching¿¿ method sustains the ability to adjust the message transmission path in the face of fast fluctuations in traffic-flow conditions. The hardware arc... View full abstract»

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  • Memory-interference model for multiprocessors based on semi-Markov processes

    Publication Year: 1987, Page(s):203 - 214
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1157 KB)

    The interference that results from processors attempting to simultaneously access the same main memory in a multiprocessor can be reduced by constructing the memory from separate modules accessible through a crossbar network. The effectiveness of this solution depends on the number of processors and the number of memory modules, and on the parameters of the computation being executed, such as the ... View full abstract»

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