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IEE Proceedings G - Electronic Circuits and Systems

Issue 4 • Date August 1987

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Displaying Results 1 - 8 of 8
  • Efficient fault diagnosis in analogue circuits using a branch decomposition approach

    Publication Year: 1987, Page(s):149 - 157
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (980 KB)

    A branch decomposition approach for fault diagnosis in analogue circuits is presented. Two fault models for the fault simulation of operational amplifier circuits are also proposed. The method uses linear fault diagnosis (FD) equations based on Kirchhoff's current law and nodevoltage measurements under the desired current excitations. The circuit is divided into subnetworks and appropriate interco... View full abstract»

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  • Network transformations for incorporating nonideal simulated immittances in the design of active filters and oscillators

    Publication Year: 1987, Page(s):158 - 166
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (991 KB)

    Although the usual methods of designing active filters through the inductance simulation and frequency dependent negative resistor (FDNR) approaches necessarily require active networks capable of simulating ideal inductors and ideal FDNRs, this paper describes network transformations which make it possible to incorporate even nonideal (lossy) simulated inductance and FDNR elements directly into th... View full abstract»

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  • New approach to the design of fir digital filters

    Publication Year: 1987, Page(s):167 - 180
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1250 KB)

    This paper presents a new approach to designing finite impulse response (FIR) digital filters. The design algorithm is based on the least mean square (LMS) criterion in the time domain to calculate the filter coefficients using the weighted gain peak errors to adjust the LMS cost function. The filter responses are optimum in the sense that the maximum gain error is minimised. The design procedure ... View full abstract»

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  • Implementation of the discrete Fourier transform on 2-dimensional systolic processors

    Publication Year: 1987, Page(s):181 - 186
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (738 KB)

    A scheme for computing the discrete Fourier transform (DFT) of a 2-dimensional systolic array processor is presented. The DFT algorithm is rewritten as a matrix based algorithm and mapped onto a 2-dimensional systolic array processor. The significance of this approach is that the total time required to complete an N-point DFT is 3¿(N) + N time units (assuming that it takes one time unit to operat... View full abstract»

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  • Multidimensional spherically symmetric recursive digital filter design satisfying prescribed magnitude and constant group delay responses

    Publication Year: 1987, Page(s):187 - 193
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (816 KB)

    A computationally efficient technique for the design of multidimensional spherically symmetric recursive digital filters satisfying prescribed magnitude and constant group delay specifications is presented. The denominator and the numerator of the transfer function are designed separately. The former is used to approximate the group delay response and the latter is used to approximate the magnitud... View full abstract»

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  • Junction charge-coupled devices for bit-level systolic arrays

    Publication Year: 1987, Page(s):194 - 198
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (733 KB)

    The application of junction chargecoupled devices (JCCDs) within the concept of bitlevel systolic arrays is discussed. The extremely small basic memory cell and the low power dissipation of CCDs make it a candidate for bit-level systolic arrays if fast suitable logic functions can be realised. Junction charge-coupled logic (JCCL) provides a good solution to the large amount of local memory. The im... View full abstract»

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  • Pole-zero pairing strategies for cascaded switched-capacitor filters

    Publication Year: 1987, Page(s):199 - 204
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (728 KB)

    The effect of pole zero pairing on the total capacitance of cascaded biquad SC filters is investigated. It is shown that significant reductions in total capacitance and hence corresponding reductions in silicon area are possible through optimal pole-zero pairing without causing significant degradations in filter performance. View full abstract»

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  • BILBO registers with nonlinear feedback

    Publication Year: 1987, Page(s):205 - 208
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (524 KB)

    Built in logic block observation (BILBO) has become one of the most widely accepted techniques for self-testing of complex digital ICs. This technique is based on grouping the storage elements of the circuit in the two registers which give this technique its name. A BILBO register has four functional modes: with each of the stages acting as independent registers; as a generator of pseudorandom seq... View full abstract»

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