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IEE Proceedings E - Computers and Digital Techniques

Issue 2 • Date March 1987

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Displaying Results 1 - 10 of 10
  • Test generation for digital circuits described by means of register transfer languages

    Publication Year: 1987, Page(s):69 - 77
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1231 KB)

    In this paper, we propose systematic procedures for generating the test sequence for digital systems described by means of procedural register transfer languages. Faults in the data unit (data faults) and in the control unit (control faults) will require different techniques for their detection. For the data unit, a graph representing the data flow, the transfer graph, is proposed. Techniques for ... View full abstract»

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  • Book review: Advanced Digital Information Systems

    Publication Year: 1987
    IEEE is not the copyright holder of this material | PDF file iconPDF (141 KB)
    Freely Available from IEEE
  • Fault diagnosis in Ben¿s switching networks

    Publication Year: 1987, Page(s):78 - 86
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1089 KB)

    Faulty switches, broken interswitch connections and certain bridging faults in a Ben¿s switching network can be identified using a sequence of faulty paths across the network. The method described may use on-line faulty-path data and is suitable for use in the diagnosis of intermittent faults. It is shown that a single faulty switch can be identified in less than four random faulty paths on avera... View full abstract»

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  • Techniques for implementing two-dimensional wafer-scale processor arrays

    Publication Year: 1987, Page(s):87 - 92
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (711 KB)

    This paper describes some of the techniques that are being used to implement a two-dimensional wafer-scale processor array. Manufacturing defects on the wafer are tolerated by using hierarchical redundancy. This strategy employs programmable links at the highest sub-system level to ensure good electrical isolation against gross defects, while lower down in the hierarchy, transistor switches are us... View full abstract»

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  • Graphical method for the conversion of minterms to Reed-Muller coefficients and the minimisation of exclusive-OR switching functions

    Publication Year: 1987, Page(s):93 - 99
    Cited by:  Papers (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (809 KB)

    A graphical method extended from a folding technique developed by Wu et al. is used to convert the minterms of a switching function to the coefficients of its Reed-Muller polynomial with fixed polarity. The conversion starts from a Karnaugh map and results in a Reed-Muller coefficient map. An algorithm which attempts to find a minimal exclusive-OR realisation for the switching function in mixed po... View full abstract»

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  • Book review: Local Area Network Design

    Publication Year: 1987
    IEEE is not the copyright holder of this material | PDF file iconPDF (185 KB)
    Freely Available from IEEE
  • Digital image registration by phase correlation between boundary maps

    Publication Year: 1987, Page(s):101 - 104
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (882 KB)

    The performance of the phase-correlation image-registration algorithm when greyscale images are replaced by boundary maps is discussed in the light of several experiments. It is found that use of contours only does not substantially degrade the algorithm performance, while the reduced amount of information associated with each image may turn to advantage whenever the bandwidth of the communication... View full abstract»

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  • Algorithm to detect reconvergent fanouts in logic circuits

    Publication Year: 1987, Page(s):105 - 111
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (849 KB)

    Testability measures have been advocated by many authors as aids in the designing and testing of logic circuits. These have been shown to be inaccurate for circuits which contain reconvergent fanouts. An algorithm is presented which will detect all sources of reconvergence in a circuit by processing a normal textual circuit description. As well as identifying all the gates at which reconvergence o... View full abstract»

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  • Algorithm for obtaining a self-synchronising M-ary code enabling data compression

    Publication Year: 1987, Page(s):112 - 118
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (729 KB)

    An algorithm for obtaining a self-synchronising M-ary code (M ¿¿ 2) enabling the compression of data from a stationary discrete memoryless source is proposed. After presenting the code algorithm, its properties are analysed and the implementation of the code is described. The code proposed is compared to the Huffman code with regard to the average code-word length, the possibility of self synchron... View full abstract»

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  • Parallel image-processing system based on the TMS32010 digital signal processor

    Publication Year: 1987, Page(s):119 - 124
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (865 KB)

    A parallel image processor (PIP) consisting of eight Texas Instruments TMS32010 digital signal processors is described. The architecture is designed for image-processing applications and two common pattern-recognition algorithms, i.e. edge detection followed by thinning are implemented achieving a total processing time of less than one second for a 256 ¿¿ 256 pixel image. The advantages and limita... View full abstract»

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