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Computers and Digital Techniques, IEE Proceedings E

Issue 1 • Date January 1987

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Displaying Results 1 - 11 of 11
  • Famnet: an integrated voice and data network

    Page(s): 1 - 8
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1077 KB)  

    The paper describes the design and implementation of the various items of equipment associated with an integrated voice and data network known as FAMNET. The equipment is intended for use with a broadband coaxial cable distribution network. The paper first outlines the mode of operation of broadband networks and this is followed by a description of the user interface to FAMNET. A description of the implementation of an RF modem for use with the network is then presented together with a description of a network monitoring system. View full abstract»

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  • Recognition of partially occluded two-dimensional objects

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1015 KB)  

    Recognition of partially occluded objects is essential for many industrial applications of machine vision. A fast and reliable algorithm based on subtemplate matching of boundary images is proposed to tackle the problem. Dynamic programming (DP) is employed in the algorithm to ensure an optimal consistent solution. With the weightings of the subtemplate determined off-line, the computational effort is roughly proportional to MN, where M is the length of image boundary and N is the number of subtemplates to be matched. Experimental results show that the algorithm will work for a wide variety of objects. View full abstract»

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  • Book review: Spectral Techniques and Fault Detection

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    Freely Available from IEEE
  • Arithmetic unit with integral division and square root

    Page(s): 17 - 23
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (790 KB)  

    Arithmetic units are usually designed to perform addition and subtraction as quickly as possible, with multiplication as a good second. Division is sometimes added later, and a few workers have proposed hardware for other mathematical functions. The paper describes an attempt to design a combined division and square-root unit, drawing on the similarities of algorithm to be seen in comparing the pencil and paper calculations. The unit which results turns out to be capable of implementing a simple multiplication algorithm, and to be capable of fixed-point addition and subtraction. Speed of division and square root are very respectable, considering the simplicity of the approach and the technology used for the implementation. A custom-IC implementation would be very cost effective. View full abstract»

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  • Partitioning concurrent VLSI simulation programs onto a multiprocessor by simulated annealing

    Page(s): 24 - 30
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (859 KB)  

    Efficiently loading concurrent programs onto multiprocessor architectures is a graph partitioning problem where both the edges and vertices are weighted. The corresponding optimisation problem is computationally NP-hard, and the optimal solution can only be found by exhaustively examining all possible partitioning configurations. Near-optimal solutions can be found by using heuristic algorithms such as iterative improvement and simulated annealing. The simulated annealing heuristic is experimentally evaluated against simple iterative improvement for graphs representing the concurrent simulation programs of four VLSI circuits where the vertices were weighted. A simple cost function and an annealing schedule are presented for partitioning the graphs onto a star network of identical processors. Experimental results show that simulated annealing produces a better solution than simple iterative improvement but at the expense of considerable computer running times. It is suggested that the time required for simulated annealing to give better solutions than iterative improvement depends on the nature of distributions of weighted vertices and edges in the concurrent simulation graph as well as its size. View full abstract»

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  • Real-time shaded colour polygon generation system

    Page(s): 31 - 38
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (975 KB)  

    The paper describes a hardware architecture for a graphics system which can generate shaded, colour, perspective 2-dimensional images of complex 3-dimensional scenes, in real time. The architecture is capable of operating at the high pixel rates required to produce scenes on rasterscan displays with high spatial resolution (1280 H by 1024 V), high colour resolution (24-bit), and high refresh rate (60 Hz non-interlaced). The architecture of the pixel rate section is described in detail. The architecture is suitable for implementation using custom VLSI techniques. View full abstract»

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  • RAPAC: a high-speed image-processing system

    Page(s): 39 - 46
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (987 KB)  

    The paper describes the design and operation of a real-time image processing system and outlines one of its application areas. The system consists of a dedicated hardware processor called RAPAC (a reconfigurable attached processor architecture for convolution) and a host computer which is used for algorithm development and RAPAC control. RAPAC uses hardware processor units and multiple image memories, in a software controlled architecture, to process 5 MHz streams of pixel data. This processing rate allows it to process a 256 ¿¿ 256 pixel image in 20 ms, one field time of a standard TV camera. The result is either a new 256 ¿¿ 256 pixel image generated from the old image or a reduced data set which describes attributes of features in the image. These attributes are used by the host computer to calculate a decision output concerning the content of the image. View full abstract»

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  • Ethernet for real-time applications

    Page(s): 47 - 53
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (857 KB)  

    Local area networks have been used successfully in data processing applications for several years. Recently, there have been several proposals for using these networks in real-time applications such as voice transmission. This project examines, by means of a simulation, the feasibility of using Ethernet for carrying data in real-time environments, and, in particular, studies the effect of channel load on network delay. The simulation described shows that, with appropriately chosen loads, Ethernet can keep within realtime constraints and service every node successfully. View full abstract»

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  • Analysis of an adaptive multiple-access protocol (ATP-1) with mixed structure

    Page(s): 54 - 60
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (884 KB)  

    In the paper a new multiple-access protocol, called ATP-1, is analysed. This protocol employs a self-adaptive scheme that switches between two states, the random-access state and the fixed-access state. The analysis is based on an embedded Markov process obtained by examining the system at the beginning of the epochs, which are defined as the intervals of random access state or fixed access state. The epoch duration depends on the number of the busy users at the beginning of the epochs. Finally, the dynamic behaviour of this new scheme is examined in detail using the Markovian properties of the two, above mentioned, protocols. View full abstract»

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  • Dynamic behaviour of a new adaptive multiple-access protocol and comparison with the split-channel reservation multiple-access protocol

    Page(s): 61 - 68
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (980 KB)  

    In the paper we discuss the dynamic behaviour of a new multiple-access protocol, the ALOHA-TDMA protocol, hereafter referred to as ATP-2. This protocol belongs to the category of the self-adaptive reservation multiple-access protocols. It uses two subchannels, the request subchannel for the user's request packets and the information subchannel for their information packets, as in the split-channel reservation multiple-access (SRMA) protocol. The first channel (the request subchannel) operates with a fixed-access protocol (round-robin or random TDMA), whereas the second (the information subchannel) combines the advantages of the two basic multiple-access protocols, the S-ALOHA and the TDMA protocols. Thus, through the information contained in the reservation subchannel minislots, the ATP-2 can be smoothly adapted to the instantaneous service needs of the users. An analytical method is described to calculate the throughput, expected delay and some important probabilities. Also, the bistable behaviour of the ATP-2 protocol under certain operation conditions is examined. Next, a comparison is made between the ATP-2 and SRMA protocol that shows the superiority of the ATP-2. Finally, we propose a hardware implementation for the nodes of a network based on the ATP-2 protocol. View full abstract»

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