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IEE Proceedings E - Computers and Digital Techniques

Issue 5 • Date September 1986

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Displaying Results 1 - 7 of 7
  • Digital design verification

    Publication Year: 1986
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | PDF file iconPDF (118 KB)
    Freely Available from IEEE
  • Specification and verification of digital systems using higher-order predicate logic

    Publication Year: 1986, Page(s):242 - 254
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1876 KB)

    The paper describes how higher-order predicate logic may be used to specify both the structure and the behaviour of a digital system, and to reason about their interrelationship. The overall approach is named VERITAS; the paper concentrates particularly on describing its methodological aspects. The behaviour of a system is specified by a predicate on the analogue waveforms at the ports of the syst... View full abstract»

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  • Formal hardware verification methodology and its application to a network interface chip

    Publication Year: 1986, Page(s):255 - 270
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1384 KB)

    We describe how the functional correctness of a circuit design can be verified by machine checked formal proof. The proof system used is LCF_LSM, a version of Milner's LCF with a different logical calculus called LSM. We give a tutorial introduction to LSM in the paper. Our main example is the ECL chip of the Cambridge fast ring (CFR). Although the ECL chip is quite simple (about 360 gates) it is ... View full abstract»

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  • Use of time functions to describe and explain circuit behaviour

    Publication Year: 1986, Page(s):271 - 275
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (511 KB)

    The paper illustrates the use of a mechanical model for describing the time behaviour of hardware. In this model, any variable is represented by a function of time, giving the value of the variable at each instant. Some tools are introduced for describing such functions, and the use of function algebra, for reasoning about hardware descriptions, is illustrated. View full abstract»

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  • Automatic verification of asynchronous circuits using temporal logic

    Publication Year: 1986, Page(s):276 - 282
    Cited by:  Papers (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (964 KB)

    A method is presented for automatically verifying asynchronous sequential circuits using temporal logic specifications. The method takes a circuit desctibed in terms of Boolean gates and Muller elements, and derves a state graph that summaries all possible circuit executions resulting from any set of finite delays on the outputs of the components. The correct behaviour of the circuit is expressed ... View full abstract»

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  • Aid to hierarchial and structured logic design using temporal logic and Prolog

    Publication Year: 1986, Page(s):283 - 294
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1272 KB)

    The paper describes a study of an aid for hardware logic design using temporal logic, called linear time temporal logic (LTTL), and Prolog. A review of specification techniques for synchronisation parts using LTTL is given. A temporal logic programming language called Tokio, which is based on LTTL and includes interval variables, is presented. As parallelisms are tedious to describe sequentially i... View full abstract»

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  • Design and verification of regular synchronous circuits

    Publication Year: 1986, Page(s):295 - 304
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1259 KB)

    A VLSI design language, µFP, is presented and it is shown how it can be used in the development of regular array circuits. The higher order functions which are used to build circuit descriptions have geometric as well as semantic interpretations. They allow common circuit forms to be described simply and concisely. The language obeys various algebraic laws, and circuits are developed by transform... View full abstract»

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