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Computers and Digital Techniques, IEE Proceedings E

Issue 2 • Date March 1986

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Displaying Results 1 - 6 of 6
  • Spectral testing of circuit realisations based on linearisations

    Publication Year: 1986 , Page(s): 73 - 78
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (733 KB)  

    Fault-detection techniques using data compression have evolved during the last few years. Two of these involve syndrome testing and spectral-coefficient testing, which are closely related to each other. It is shown in the paper that, for combinational circuits designed using a linearisation method proposed by a number of authors, it is always possible to cover all single stuck-at faults using a linearisation signature that consists of m + 1 spectral coefficients (m < n, the number of input variables). It is also shown that the linearisation signature provides some coverage against multiple faults in the circuit. View full abstract»

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  • Processor failure recovery for a resource sharing algorithm

    Publication Year: 1986 , Page(s): 79 - 86
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (984 KB)  

    With the increase in popularity of distributed computer systems, the reliability of the system as a whole is becoming more important. A recently published combined resource sharing algorithm showed how the atomic operations required for resource management in a closely coupled multiprocessor system could be provided. The paper describes a recovery system that may be incorporated within the earlier algorithm to enable continued and correct operation of the system despite the failure of one or more component processors. A distributed simulation of the recovery mechanism is described and results from simulation runs are presented. View full abstract»

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  • Parallel algorithm for shortest paths

    Publication Year: 1986 , Page(s): 87 - 93
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1182 KB)  

    An algorithm for finding a shortest path between each pair of nodes of a positive arc weighted graph on a shared memory model of a single instruction-stream multiple data-stream computer is proposed. The time complexity of the algorithm is of O(log d . log n), where d and n denote the diameter and the number of nodes of the graph, respectively. At most, O(n3) processors are required to achieve this time bound. View full abstract»

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  • Secret-hardware public-key cryptography

    Publication Year: 1986 , Page(s): 94 - 96
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (302 KB)  

    The paper presents the concept of secret-hardware public-key (SHPK) cryptography which allows the design of efficient systems, provided there exists a trusted central authority to generate key pairs. A realisation of a SHPK system based on exponentiation is presented. View full abstract»

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  • Technical memorandum. Digital linear transducer using a dynamic RAM

    Publication Year: 1986 , Page(s): 97 - 99
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    A dynamic RAM can form the basis of a low-cost digital position sensor. The theory of operation of such a device is presented, and experimental results for a prototype DRAM-based transducer are discussed. View full abstract»

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  • APL: an effective design language

    Publication Year: 1986 , Page(s): 100 - 104
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (745 KB)  

    The paper describes the use of APL (a programming language) for the specification of a hardware architecture, the description of an initial implementation algorithm, its verification and controlled transformation to a logic design. Because of its power of expression, APL can be used effectively in each of these design domains. The APL interpreter turns any description into an executable prototype. Such a prototype is a powerful tool in the management and execution of a design; it clarifies design choices and assures the logical correctness of the product. This computer-aided-design process, which is illustrated by the design of the front end of a logic analyser, is useful for a variety of design situations, such as LSI/VLSI and computer design. View full abstract»

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