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Computers and Digital Techniques, IEE Proceedings E

Issue 6 • Date November 1984

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Displaying Results 1 - 6 of 6
  • Microprogrammable sequential controller

    Page(s): 201 - 208
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1100 KB)  

    The architecture and design of a high-performance general-purpose microprogrammable sequential controller are presented. Conventional logic controllers are limited by speed, memory requirements or flexibility and programming ease. The requirements of a basic sequential controller are identified, and a memory segmentation technique is proposed for efficient data structuring. A parallel-architecture sequential controller is designed so that it is both fast and memory efficient. The new controller has a fixed hardware and is microprogrammable through firmware modification. It is especially designed for complex high-speed sequential controllers requiring large I/O capabilities. View full abstract»

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  • Design and evaluation of the event-driven computer

    Page(s): 209 - 222
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1799 KB)  

    This paper describes a new design methodology for a class of next-generation computers. Our proposal, the event-driven computer (EDC), is primarily a data-driven heterogeneous system which is supplemented with control-driven activities; such a combined approach is aimed at extracting the advantages of both the `pure¿ data-driven and control-driven systems while alleviating their shortcomings. Compared to other similar designs EDC has the advantages of a better resource utilisation, array processing capabilities and a higher speed range. The hardware architecture, language features and performance evaluation are discussed. A recently developed loop-structured interconnection network is modified for this application; with a configuration of 64 loops, it can connect up to approximately 400 processors, and hence an execution speed of more than 1000 MOPS can be obtained. View full abstract»

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  • Hardware for real-time image processing

    Page(s): 223 - 229
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (806 KB)  

    The system described here is a real-time edge detector for use in image processing. The edge-detection algorithm is a 2 ¿¿ 2 Roberts product, thresholded with a function of the local average brightness. The hardware is designed to work at 10 MHz pixel rate, and will accommodate images of 512 ¿¿ 512 pixels at 25 frames/s with noninterlaced video, or of up to 512 ¿¿ 290 pixels with interlaced scanning. The hardware is pipelined and paralleled to achieve the required speed. The output from the system is a one-bit-per-pixel edge picture. This is transferred directly into the memory of the host computer for further processing. View full abstract»

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  • VLSI¿evolution or revolution

    Page(s): 230 - 233
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (682 KB)  

    An evaluation of the impact of VLSI on manufacturing, design techniques and design methods of electronic digital systems is presented. Also, possible future trends resulting from the impact of VLSI are pointed out. A comparison with the pre-VLSI state-of-the-art technology is used. View full abstract»

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  • Conference report. 14th IEEE international symposium on multiple-valued logic

    Page(s): 233 - 234
    Save to Project icon | PDF file iconPDF (276 KB)  
    Freely Available from IEEE
  • Erratum: Editorial

    Save to Project icon | PDF file iconPDF (127 KB)  
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