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Electronic Circuits and Systems, IEE Proceedings G

Issue 2 • Date April 1984

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Displaying Results 1 - 11 of 11
  • Design procedure for high-stability four-crystal single-sideband lattice filters with equiripple or maximally flat passbands and double attenuation poles at finite frequencies

    Page(s): 37 - 45
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (897 KB)  

    A lowpass second-order Cheby¿shev or Butterworth filter is converted into a fourth-order filter with an equiripple or maximally flat passband and a double attenuation pole at a finite frequency using the Zdunek- Möbius transformation. The double pole enables the filter to be realised as a single lattice with an identical crystal in each arm resonating at the pole frequency. Transferring these crystals to outside the lattice results in filters with a very stable transition band, since the pole frequency now depends only on crystal frequencies, whose variation is several orders of magnitude less than the variation of lumped inductors and capacitors which influence the pole frequency in a conventional crystal filter. The transformation by Zdunek for doubling the circuit order is not applied in the usual manner to obtain a higher-order characteristic of a similar type. Instead, it is used here to obtain a characteristic which is unconventional as a result of the double attenuation pole. This application is not restricted to crystal filters. The symmetrical to asymmetrical transformation is applicable to other type of bandpass crystal filter. View full abstract»

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  • Computationally efficient circularly symmetric two-dimensional FIR filters

    Page(s): 46 - 50
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (710 KB)  

    An efficient technique is presented for synthesising and implementing narrowband circularly symmetric two-dimensional finite-impulse-response digital filters. The technique is based on a special case of the generalised McClellan transformations, and it uses an efficient implementation proposed by McClellan and Chan for filters designed via the transformation method. The transformation is constructed in such a way that the requirements for the prototype one-dimensional filter are much alleviated, and the subnetworks implementing the transformation require no multipliers and only a few adders. Examples show how the new filter implementations require, in narrowband applications, significantly less multiplications and additions per output sample than equivalent filters designed using the original transformation of McClellan. View full abstract»

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  • New general biquadratic active RC and switched-capacitor filters

    Page(s): 51 - 55
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (481 KB)  

    An active RC filter capable of realising a general biquadratic transfer function, using two operational amplifiers with grounded noninverting inputs, is described. Its application to the realisation of SC filters using `p-transformation¿ is also discussed. View full abstract»

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  • Part 1: VLSI implementation of an optimised hierarchical multiplier

    Page(s): 56 - 60
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (531 KB)  

    The implementation and optimisation procedure of a regular, and recursive, high-speed N-bit multiplier design is presented. The design comprises two simple cells: a 2 × 2-bit multiplier PLA and a full adder PLA, and most of the interconnections are local and regular. Extension of the design to any multiplier word size can be done by simply combining smaller cell blocks following the same algorithm. The multiplier is optimised for area-time complexity, using the analysis presented in Part 2, and its performance relative to previously reported designs is good. A four-bit multiplier implementation is discussed in detail. View full abstract»

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  • Part 2: An optimising analysis of hierarchical multipliers for VLSI

    Page(s): 61 - 66
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (570 KB)  

    An analysis of area-time complexity is presented for a specific hierarchical-multiplier design. The analysis is generally applicable to a variety of multiplier designs having hierarchical structure and may be used as a basic analytical tool for other arithmetic structures with hierarchy. Area and time performance are derived in terms of branching ratio, and it is found the optimal area-time complexity is obtained for a branching ratio of four. View full abstract»

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  • Transfer-function realisation of a class of doubly terminated two-variable lossless networks and their application in two-dimensional analogue and digital filter design

    Page(s): 67 - 71
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    The method used in the design of two-dimensional wave digital filters is to employ appropriate analogue reference filters. The analogue filters often used for this purpose are doubly terminated two-variable lossless two-port networks, since they are well known for their low sensitivity under coefficient quantisations. In this paper, necessary and sufficient conditions are given under which a two-variable rational function can be realised as the transfer function of a doubly terminated cascade of p1- and p2-variable lossless two-ports, each two-port having all of its transmission zeros at the origin or infinity. Using these conditions, the transfer function of a two-variable analogue reference filter is generated. Parameters of this transfer function are then used as variables of optimisation to minimise the least-mean-square error between the amplitude response of the ideal and designed filters. The discrete version of the filter is obtained by the application of a bilinear transformation to the designed analogue reference filter. To illustrate the method an example is given. View full abstract»

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  • Signal-flow graph analysis of SC networks

    Page(s): 72 - 85
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1267 KB)  

    Using well known signal-flow graph techniques, the closed-form analysis of switched-capacitor (SC) networks is shown to be straightforward and simple. The method is based on an extension of the already established four-port and multiport analysis of SC networks via the transmission matrix. Tables of commonly used SC networks, in which the corresponding signal-flow graphs are given, make the analysis readily applicable to most types of SC networks, including complex biquads and ladder networks. The method is also a useful tool for the synthesis of new SC circuits. View full abstract»

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  • Decimation technique for optimal data transfer in one- and two-dimensional FIR digital-filter implementations

    Page(s): 86 - 89
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    A general decimation technique to optimise (i.e. minimise) data transfer in the implementation of one-dimensional and two-dimensional FIR filters is presented. The approach is particularly significant when the implementation consists of multiplier arrays connected to a micro/minicomputer. The scheme significantly improves processing speed. For 100 × 100 2-dimensional array, the required data transfer is reduced from 10000 to 200. View full abstract»

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  • Design of High-Performance Negative-Feedback Amplifiers

    Save to Project icon | PDF file iconPDF (180 KB)  
    Freely Available from IEEE
  • Broadband Feedback Amplifiers

    Page(s): 90 - 91
    Save to Project icon | PDF file iconPDF (288 KB)  
    Freely Available from IEEE
  • Illustrated Guidebook to Electronic Devices and Circuits

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    Freely Available from IEEE