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Computers and Digital Techniques, IEE Proceedings E

Issue 6 • Date November 1982

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Displaying Results 1 - 6 of 6
  • On a property of the Chrestenson spectrum

    Page(s): 217 - 222
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (765 KB)  

    It is shown that two p-valued functions may be multiplexed into a complex function which has a Chrestenson spectrum. Demultiplexing in the spectral domain is simple and lends itself to parallel processing. A particular form of symmetry of the Chrestenson spectrum allows one to take advantage of the increase in information density obtained by multiplexing. View full abstract»

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  • Multiprocessor implementation of the logic function of a multiplexed wiring system for automotives

    Page(s): 223 - 228
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (806 KB)  

    The problems of conventional automotive wiring harnesses and how they can be minimised by multiplexing are discussed. The multiplexed wiring harness replaces the conventional harness with a cable bus carrying power and time-division multiplexed control signals to electronic modules that decode the control signals and activate power switches accordingly. An experimental multimicrocomputer multiplexing system is described. It has a centralised processing unit (CPU) and up to eight local processing units (LPU) interconnected to the cable bus. The electronic harness is controlled by the CPU which processes all inputs to the system and then transmits commands to the LPUs for control of each function of the electrical system. The CPU is located in close proximity to the dashboard and the majority of control inputs are directly wired into the CPU board. The LCUs are located in areas of high load density in the vehicle. Connections between the LPUs and the peripheral electrical equipment are made by small subharnesses, in most cases by a single fly lead. An LPU will only respond to a command signal from the CPU when the command address and its own address match. To eliminate the problem of spurious commands occurring owing to electrical interference, the CPU employs the repeated transmission method for communication. The switching channels have two commands associated with them: one to turn on and one to turn off. Following reception of these commands, there is a time slot available during which the LPU sends back to the CPU diagnostic information relating to the performance of the load controlled by the channel. The system incorporates a number of failsafe features to avoid potentially dangerous situations arising in the event of a CPU failure or damage occurring to the system. View full abstract»

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  • Fault detection and correction in array computers for image processing

    Page(s): 229 - 234
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (941 KB)  

    The paper addresses the problems of detecting and correcting faults that may occur in arrays of processors used for image processing. The variety of useful hardware and software solutions is reviewed. It is shown that faults can be corrected efficiently by bypassing the faulty column of the array, and a novel technique is described which detects processor faults with a very modest increase in circuitry. The addition of a parity check on the memory is sufficient to give an effective and efficient detection and correction of all permanent and many transient faults. Additionally, the use of a full parity processor increases the proportion of transient faults detected. View full abstract»

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  • Efficient addressing scheme for sequentially accessed serial highways

    Page(s): 235 - 238
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (421 KB)  

    It is now common practice in industrial applications of digital electronics for plant interface units to be geographically distributed and connected to a central point by a time-division multiplexed serial link. As in all such links, some means must be provided for each interface unit to send or accept data only in its allotted time, and the paper describes an arrangement which minimises the time consumed by this addressing function without sacrificing reliability in noisy environments. It entails the central station sending one bit of address information in each unit's time slot, in such a way that the current n-bit address is formed by the n most recently received address bits. Each unit can verify this process. The method is suitable for applications, in which many remote units are scanned sequentially to exchange data with a central station; for example, in datalogging. View full abstract»

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  • Realisation of logic functions by multi-output threshold-logic gates

    Page(s): 239 - 243
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    Two different multi-output threshold-logic gate structures are considered and their information requirements compared. A method, based on a trial and error algorithm, is described which may be used to realise a logic function by each of these structures. The method is quite general and has been tested on a large number of functions. Some preliminary observations from these tests are presented. View full abstract»

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  • Book review: Digital Logic Design

    Save to Project icon | PDF file iconPDF (146 KB)  
    Freely Available from IEEE