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IEE Proceedings I - Solid-State and Electron Devices

Issue 2 • Date April 1988

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Displaying Results 1 - 3 of 3
  • Influence of gallium in a metallisation on GaAs

    Publication Year: 1988, Page(s):25 - 28
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (422 KB)

    ESCA analysis of systems composed of Ge, Ga, Au layers alloyed to GaAs is reported to elucidate the influence of gallium in a metallisation scheme. The results reveal that a metal system containing gallium shows an absence of arsenic in the alloyed surface, and thus its presence precludes an early dissociation of GaAs. The metallurgical analyses are correlated to previously reported unstable perfo... View full abstract»

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  • CAD for VLSI: Symple: a symbolic layout tool for bipolar and MOS VLSI

    Publication Year: 1988, Page(s):29 - 38
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1158 KB)

    Symbolic layout offers a powerful and flexible methodology for the design of bipolar and MOS cells. An integrated set of symbols that addresses both bipolar and MOS devices was previously reported. A design tool that implements the symbolic methodology based on that set has been developed; Symple is a processindependent layout editor that allows the designer to symbolically create cells in bipolar... View full abstract»

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  • General experimental method of parameter extraction for CMOS timing macromodels

    Publication Year: 1988, Page(s):39 - 47
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1061 KB)

    A new general experimental method for timing macromodel parameter extraction is proposed and investigated. Based on the general timing models developed and the measured timing data of CMOS inverters, the critical field exponent UEXP of carrier mobilities in transient operation, the optimal gate/source voltage and pn-junction voltage, and the capacitances associated with a logic gate are extracted ... View full abstract»

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