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Solid-State and Electron Devices, IEE Proceedings I

Issue 5 • Date October 1980

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Displaying Results 1 - 13 of 13
  • Semiconductor laser analysis: general method for characterising devices of various cross-sectional geometries

    Page(s): 221 - 229
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (823 KB)  

    A formalism for the analysis of semiconductor lasers is described. The treatment includes the interaction between the optical field and the gain profile and thus allows the question of mode stability to be examined. The method of analysis is sufficiently flexible to allow the characterisation of a wide range of devices with varying cross-sectional geometries. In particular, there is no requirement that symmetric structures must be specified to allow analysis. The use of the procedure is illustrated by application to the stripe geometry laser. View full abstract»

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  • General model for defect formation in silicon dioxide

    Page(s): 230 - 234
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (594 KB)  

    This paper proposes a general model for the formation of the defects, in silicon dioxide, which conforms to existing concepts involved in the migration of ions through SiO2 and confirms Peek's law. Furthermore the interrelationship between the time required for the formation of any number of defects and the applied electric field is shown to be consistent with the presence of space charge limited ion currents in the oxide. Such currents are shown to give rise to enhanced Fowler-Nordheim emission of electrons into the oxide. In developing the model, a boundary layer approximation is used. The present results are consistent with the presence of large amounts of trapped mobile ions in the boundary layer. Such traps would lead to a boundary layer of which the thickness does not vary with time and which acts as a plentiful supply of mobile ions. View full abstract»

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  • Gain/bandwidth predictions for travelling-wave gyrotron

    Page(s): 235 - 240
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    The small signal gain of a travelling-wave gyrotron is computed using a Pierce description of the interaction between a `fast¿ waveguide mode and a relativistic gyrating electron beam. The mathematical model assumes a matched device containing some selective loss so that moding and backward-wave oscillation problems can be neglected. Whereas from a practical standpoint this simplification may appear excessive, the computed results nevertheless help to expose the basic nature of the amplifying process. View full abstract»

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  • Gunn oscillations in thin GaAs epilayers and m.e.s.f.e.t.s

    Page(s): 241 - 249
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    Oscillations due to travelling Gunn domains have been observed in gated and ungated GaAs m.e.s.f.e.t.s (channels) made on v.p.e. and l.p.e. active layers. The doping was 1-2 × 1017 cm ¿3 and the thickness 0.1-0.2 ¿m. In channels with non-negative I/V slope the oscillators were possible only with pulsed bias and decayed 1¿3 ns after switching on the bias. In f.e.t.s the oscillations were self sustained, delivered approximately 60 ¿W r.f. power on 50 ¿ and their frequency in the range 16¿27 GHz was predicted, as in the channels, by the length of the drain to source gap, The domain formation is sensitive on the cross section of the epilayer and the microstructure of the ohmic contacts. View full abstract»

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  • Computer technique for solving schottky barrier from dark forward current-voltage characteristics

    Page(s): 250 - 252
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (281 KB)  

    The paper describes a computer technique for determining series resistance, shunt conductance, saturation current, ideality factor, and hence the apparent barrier height of metal-semiconductor devices from dark forward current characteristics using a least-squares fitting of experimental measurements with a theoretical model. The model used is based on the thermionic theory, incorporating both series and shunt resistance effects. View full abstract»

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  • Introduction to focused section: Developments in high-speed integrated semiconductor devices

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    Freely Available from IEEE
  • Device and circuit trends in gigabit logic

    Page(s): 254 - 265
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2048 KB)  

    Recent implementations of Gbs¿1 integrated circuits are mentioned and used as the basis for a capability projection of the more promising technologies. After first describing the projection strategy, both the silicon and GaAs circuit families are assessed with regard to their performance limits. A shorter analysis of Josephson technology follows. For scaled down devices in silicon as well as several GaAs technologies, potential l.s.i. solutions with 2¿3 GHz clock frequencies are prognosticated. The 3¿6 GHz range should eventually be accessible to m.s.i. d.m.e.s.f.e.t. circuits, whereas GaAs s.d.f.l., j.f.e.t. and e.m.e.s.f.e.t. approaches promise v.l.s.i. complexity between 1 and 3 GHz. The range around 10 GHz appears to be solely a future domain of Josephson circuits (up to v.l.s.i). View full abstract»

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  • Gallium arsenide review: past, present and future

    Page(s): 266 - 269
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (579 KB)  

    The tremendous growth of communications systems in recent years has put a demand on the electronics industry to provide higher speed integrated circuits than are currently available with today's silicon technology. To help meet this demand, the electronics industry is developing new semiconductor materials such as gallium arsenide which already report clock frequencies of 1-3 GHz in GaAs integrated circuits. There have been many exciting breakthroughs in GaAs technology in the last five years including ion implantation techniques, annealing, lithography, circuit design, GaAs materials, and GaAs i.c. testing. Within the next five years GaAs is forecast to be a dominant technology in many high speed applications. View full abstract»

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  • A 3.5 GHz self-aligned single-clocked binary frequency divider on GaAs

    Page(s): 270 - 277
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (854 KB)  

    A fully planar self-aligned technology has been ultilised to fabricate a monolithic single-clocked binary frequency divider consisting of a gated master/slave flip-flop and a complementary clock-pulse generator to drive it. An optimised version of the gated m.s. flip-flop is presented along with the m. e.s.f.e.t.model used for the simulations. Correct counting from d.c. up to 5.5 GHz for the gated m.s. flip-flop and up to 3.5 GHz for the single-clocked divider are reported. The performance and evaluation of the circuits are dealt with in detail. View full abstract»

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  • Charge-coupled devices in gallium arsenide

    Page(s): 278 - 286
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1076 KB)  

    The electronic properties of GaAs and their implications to device performance have been the subject of discussion for some time, and discrete devices such as diodes and f.e.t, with performance exceeding that which has been achieved in similar silicon devices, are commercially available. Recent advances in GaAs material and processing technologies have made possible the realisation of integrated devices with substantial complexity which have demonstrated greater speed and lower power dissipation than equivalent silicon devices. Digital integrated circuits with sub-100 ps propagation delay and power dissipation compatible with large scale integration have been demonstrated. In this paper, we describe a GaAs charge-coupled device which has demonstrated some of the attributes expected from GaAs devices of this type. This device has been operated at fcl = 500 MHz which is faster than any other ccd. Design considerations and application areas for this device are discussed. View full abstract»

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  • Low pinch-off voltage f.e.t. logic (l.p.f.l.): I.s.i. oriented logic approach using quasinormally off GaAs m.e.s.f.e.t.s.

    Page(s): 287 - 296
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1102 KB)  

    A new l.s.i. oriented logic approach, low pinch-off voltage f.e.t. logic (l.p.f.l.), leading to highly versatile logic gates capable of combining high speed and low power consumption and requiring a standard fabrication process, is introduced and structures of complex logic gates realisable with this approach are described. Furthermore, a tentative comparison of the l.p.f.l. approach with other m.e.s.f.e.t. logic approaches to date is presented to show their respective design trade-offs which dictate the range of applications open to each of these approaches. The comparison is based on both computer simulations and experimental measurements on test circuits such as ring oscillators, flip-flops and binary frequency dividers. View full abstract»

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  • Capacitor coupling of GaAs defletion-mode f.e.t.s.

    Page(s): 297 - 300
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (501 KB)  

    Integration of GaAs depletion mode f.e.t.s requires voltage level shifting between logic stages. Capacitor coupling provides such a shift without the need for additional power rails and with a high tolerance of process parameter variations; being passive, the level shifting consumes no additional power. Data can also be retained dynamically on capacitors in clocked circuits providing exceptionally low power operation. Test circuits have been fabricated which have demonstrated successfully the principles of capacitor coupling. Data from these are being used to design capacitor-coupled logic (c.c.I.) circuits for telecommunication applications. When static operation is essential, capacitor coupling can also be used to enhance the operation of conventionally coupled circuits. View full abstract»

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