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Nuclear Science, IEEE Transactions on

Issue 4 • Date Aug. 2008

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Displaying Results 1 - 25 of 67
  • [Front cover]

    Page(s): C1
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    Freely Available from IEEE
  • IEEE Transactions on Nuclear Science publication information

    Page(s): C2
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    Freely Available from IEEE
  • Table of contents

    Page(s): 1801 - 1804
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    Freely Available from IEEE
  • RADECS 2007 Conference Overview

    Page(s): 1805 - 1806
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    Freely Available from IEEE
  • Freely Available from IEEE
  • List of reviewers

    Page(s): 1808 - 1809
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    Freely Available from IEEE
  • The Near-Earth Space Radiation Environment

    Page(s): 1810 - 1832
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4246 KB) |  | HTML iconHTML  

    The effects of the space radiation environment on spacecraft systems and instruments are significant design considerations for space missions. Astronaut exposure is a serious concern for manned missions. In order to meet these challenges and have reliable, cost-effective designs, the radiation environment must be understood and accurately modeled. The nature of the environment varies greatly between low earth orbits and higher earth orbits. There are both short-term and long-term variations with the phase of the solar cycle. In this paper we concentrate mainly on charged particle radiations in the near-Earth region. Descriptions of the radiation belts and particles of solar and cosmic origin are reviewed. An overview of the traditional models is presented accompanied by their application areas and limitations. This is followed by discussion of some recent model developments. View full abstract»

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  • Radiation Effects in MOS Oxides

    Page(s): 1833 - 1853
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1872 KB) |  | HTML iconHTML  

    Electronic devices in space environments can contain numerous types of oxides and insulators. Ionizing radiation can induce significant charge buildup in these oxides and insulators leading to device degradation and failure. Electrons and protons in space can lead to radiation-induced total-dose effects. The two primary types of radiation-induced charge are oxide-trapped charge and interface-trap charge. These charges can cause large radiation-induced threshold voltage shifts and increases in leakage currents. Two alternate dielectrics that have been investigated for replacing silicon dioxide are hafnium oxides and reoxidized nitrided oxides (RNO). For advanced technologies, which may employ alternate dielectrics, radiation-induced voltage shifts in these insulators may be negligible. Radiation-induced charge buildup in parasitic field oxides and in SOI buried oxides can also lead to device degradation and failure. Indeed, for advanced commercial technologies, the total-dose hardness of ICs is normally dominated by radiation-induced charge buildup in either parasitic field oxides and/or SOI buried oxides. Heavy ions in space can also degrade the oxides in electronic devices through several different mechanisms including single-event gate rupture, reduction in device lifetime, and large voltage shifts in power MOSFETs. View full abstract»

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  • Modeling and Simulation of Single-Event Effects in Digital Devices and ICs

    Page(s): 1854 - 1878
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1778 KB) |  | HTML iconHTML  

    This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits, with a special emphasis on the current challenges concerning the physical modeling of ultra-scaled devices (in the deca-nanometer range) and new device architectures (Silicon-on-insulator, multiple-gate, nanowire MOSFETs). After introducing the classification and the terminology used in this paper, we firstly present the basis of the different transport models used in device-level simulation (drift-diffusion, hydrodynamic, Monte-Carlo and some approximated and exact quantum-mechanical based approaches). We also focus on the main emerging physical phenomena affecting ultra-short MOSFETs (quantum effects, tunneling current, ballistic operation) and the methods envisaged for taking them into account at device simulation level. Several examples of device simulation are given at the end of this first part, including recent results on fully-depleted SOI and multiple-gate devices. In the second part, we briefly survey the different circuit-level modeling approaches (circuit-level simulation, Mixed-Mode, 3-D simulation of portions of circuits) of single-event effects in integrated circuits. The SEU in advanced SRAM and SEE mechanisms in logic circuits are reminded. The production and propagation of digital single-event transients (DSETs) in sequential and combinational logic, as well as the soft error rate trends with scaling are particularly addressed. Recent bibliographical examples of simulation in SRAMs and logic circuits are presented and discussed to illustrate these topics at circuit-level. View full abstract»

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  • Modeling Single Event Transients in Bipolar Linear Circuits

    Page(s): 1879 - 1890
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1045 KB) |  | HTML iconHTML  

    This review paper covers modeling of single event transients (SETs) in bipolar linear circuits. The modeling effort starts with a detailed circuit model, in a program such as SPICE, constructed from a photomicrograph of the die, which is verified by simulating the electrical response of the model. A description of various approaches to generating the single event strike in a circuit element is then given. Next, validating and calibrating the output SET response for critical circuit transistors is discussed, using focused ions beams or lasers. The circuit model is validated with a heavy ion broadbeam to generate the output SET response in terms of SET peak amplitude versus full width half maximum pulse width. Finally, a system application is described and a ldquofailure raterdquo in space is calculated, based on the experimental heavy ion data, for a geostationary orbit using CREME96. View full abstract»

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  • Multi-Scale Simulation of Radiation Effects in Electronic Devices

    Page(s): 1891 - 1902
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1035 KB) |  | HTML iconHTML  

    As integrated circuits become smaller and more complex, it has become increasingly difficult to simulate their responses to radiation. The distance and time scales of relevance extend over orders of magnitude, requiring a multi-scale, hierarchical simulation approach. This paper demonstrates the use of multi-scale simulations to examine two radiation-related problems: enhanced low-dose-rate sensitivity (ELDRS) in bipolar transistors and single-event effects (SEE) in CMOS integrated circuits. Examples are included that demonstrate how information can be passed from simulation tools operating at one level of abstraction to those operating at higher levels, while maintaining accuracy and gaining insight. View full abstract»

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  • Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology

    Page(s): 1903 - 1925
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2304 KB) |  | HTML iconHTML  

    Increased space system performance is enabled by access to high-performance, low-power radiation-hardened microelectronic components. While high performance can be achieved using commercial CMOS foundries, it is necessary to mitigate radiation effects. This paper describes approaches to fabricating radiation-hardened components at commercial CMOS foundries by the application of novel design techniques at the transistor level, the cell level, and at the system level. This approach is referred to as hardness-by-design. In addition, trends in the intrinsic radiation hardness of commercial CMOS processes will be discussed. View full abstract»

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  • Total Ionizing Dose and Single Event Effects Hardness Assurance Qualification Issues for Microelectronics

    Page(s): 1926 - 1946
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1534 KB) |  | HTML iconHTML  

    The radiation effects community has developed a number of hardness assurance test guidelines to assess and assure the radiation hardness of integrated circuits for use in space and/or high-energy particle accelerator applications. These include test guidelines for total dose hardness assurance qualification and single event effects (SEE) qualification. In this work, issues associated with these hardness assurance test guidelines are discussed. For total dose qualification, the main test methodologies used in the U.S. and Europe are reviewed and differences between the guidelines are discussed. In addition, some key issues that must be considered when performing total dose hardness assurance testing are addressed. Following these discussions we review some emerging issues relevant to SEE device qualification that are not covered in present SEE test guidelines. The hardness assurance implications of these issues are addressed. View full abstract»

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  • Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems

    Page(s): 1947 - 1952
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (974 KB) |  | HTML iconHTML  

    A scan flip-flop (FF) is designed to observe both single event transient (SET) and single event upset (SEU) soft errors in logic VLSI systems. The SET and SEU soft errors mean the upset caused by latching an SET pulse that originates in combinational logic blocks and the upset caused by a direct ion hit to the FF, respectively. An irradiation test method using the scan FF is proposed to obtain SET and SEU soft-error rates at each FF distributed in logic VLSI systems. A test chip is designed using a 0.2-mum fully-depleted silicon-on-insulator standard cell library. The basic concepts have been validated with Verilog timing simulations. The cell-level implementation costs of the proposed scan FF are estimated to be reasonable. View full abstract»

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  • Total Dose Effects in Op-Amps With Compensated Input Stages

    Page(s): 1953 - 1959
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (702 KB) |  | HTML iconHTML  

    This paper discusses total dose damage in operational amplifiers with compensated input stages. The impact of this design approach on unit-to-unit variability of radiation damage is examined, along with hardness assurance methods that can be used to bound the radiation behavior. Data is included for an unusually large sample (100 devices) of one device type. Half of those devices were subjected to burn-in before irradiation to investigate the effect of burn-in on radiation response. View full abstract»

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  • Channel Hot Carrier Stress on Irradiated 130-nm NMOSFETs

    Page(s): 1960 - 1967
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (635 KB) |  | HTML iconHTML  

    We investigate how X-ray exposure impact the long term reliability of 130-nm NMOSFETs as a function of device geometry and irradiation bias conditions. This work focuses on electrical stresses on n-channel MOSFETs performed after irradiation with X-ray up to 136 Mrad(SiO2) in different bias conditions. Irradiation is shown to negatively affect the degradation during subsequent hot carrier injection. Increasing the bias during irradiation slightly reduces the impact on following electrical stress in core MOSFETs. Through device simulations, we attribute these effects to an enhanced impact ionization at the bulk-STI interfaces due to radiation-induced trapped charge and defects. View full abstract»

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  • Effectiveness of TMR-Based Techniques to Mitigate Alpha-Induced SEU Accumulation in Commercial SRAM-Based FPGAs

    Page(s): 1968 - 1973
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    We present an experimental analysis of alpha-induced soft errors in 90-nm low-end SRAM-based FPGAs. We first assess the relative sensitivity of the configuration memory bits controlling the different resources in the FPGA. We then study how SEU accumulation in the configuration memory impacts on the reliability of unhardened and hardened-by-design circuits. We analyze different hardening solutions comprising the use of a single voter, multiple voters, and feedback voters implemented with a commercial tool. Finally, we present an analytical model to predict the failure rate as function of the number of bit-flips in the configuration memory. View full abstract»

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  • Study of Single-Event Transients in High-Speed Operational Amplifiers

    Page(s): 1974 - 1981
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (483 KB) |  | HTML iconHTML  

    This paper presents a simulation and experimental study of the analog single-event transient sensitivity of wide bandwidth operational amplifiers. Architecture effects are presented that could influence ASIC design and COTS selection. View full abstract»

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  • Evaluation of Recent Technologies of Nonvolatile RAM

    Page(s): 1982 - 1991
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1760 KB) |  | HTML iconHTML  

    Two types of recent nonvolatile random access memories (NVRAM) were evaluated for radiation effects: total dose and single event upset and latch-up under heavy ions and protons. Complementary irradiation with a laser beam provides information on sensitive areas of the devices. View full abstract»

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  • Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

    Page(s): 1992 - 2000
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point. View full abstract»

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  • Temperature Effect on Heavy-Ion-Induced Single-Event Transient Propagation in CMOS Bulk 0.18 \mu m Inverter Chain

    Page(s): 2001 - 2006
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (716 KB) |  | HTML iconHTML  

    Heavy-ion-induced single-event transients (SET) are studied by device simulation on an ATMEL spatial component: the CMOS bulk 0.18 mum inverter. The wide temperature range of a spatial environment (from 218 to 418 K) can modify the shape of the SET. Thus, an investigation of the SET propagation through a 10-inverter logic chain is performed in the 218-418 K temperature range, and the threshold LET (LETth) required for unattenuated propagation through the inverter chain is determined. The LETth is calculated for two different locations of the heavy ion impact and for three temperature values. An increase of the sensitivity is found when the temperature is raised from 218 to 418 K. View full abstract»

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  • Probing SET Sensitive Volumes in Linear Devices Using Focused Laser Beam at Different Wavelengths

    Page(s): 2007 - 2012
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (806 KB) |  | HTML iconHTML  

    The main objective of the work presented here is to explore the ability of laser irradiations to determine the SET sensitive depths of a linear device by using several wavelengths. Laser testing at two wavelengths allows the estimation of sensitive depths. The approach conducted here is applied for the first time to a linear device with very deep sensitive depth. The 1064 nm wavelength seems to be the most adequate one to reveal all sensitive areas and, when comparing with heavy ion experimental data, shows a reasonable agreement with heavy ion cross section. View full abstract»

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  • Use of Code Error and Beat Frequency Test Method to Identify Single Event Upset Sensitive Circuits in a 1 GHz Analog to Digital Converter

    Page(s): 2013 - 2018
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (423 KB) |  | HTML iconHTML  

    Typical test methods for characterizing the single event upset performance of an analog to digital converter (ADC) have involved holding the input at static values. As a result, output error signatures are seen for only a few input voltage and output codes. A test method using an input beat frequency and output code error detection allows an ADC to be characterized with a dynamic input at a high frequency. With this method, the impact of an ion strike can be seen over the full code range of the output. The error signatures from this testing can provide clues to which area of the ADC is sensitive to an ion strike. View full abstract»

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  • A New Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-Based FPGAs

    Page(s): 2019 - 2027
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (694 KB) |  | HTML iconHTML  

    In this paper we present an analytical analysis of the fault masking capabilities of triple modular redundancy (TMR) hardening techniques in the presence of multiple cell upsets (MCUs) in the configuration memory of SRAM-based field-programmable gate arrays (FPGAs). The analytical method we developed allows an accurate study of the MCUs provoking domain crossing errors that defeat TMR. From our analysis we have found that most of the failures affect configurable logic block's routing resources. The experimental analysis has been performed on two realistic case study circuits. Experimental results are presented and discussed showing in particular that 2-bits MCUs may corrupt TMR 2.6 orders of magnitude more than single cell upsets (SCUs). View full abstract»

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  • New Analytical Solutions of the Diffusion Equation Available to Radiation Induced Substrate Currents Modeling

    Page(s): 2028 - 2035
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1106 KB) |  | HTML iconHTML  

    This paper describes some new solutions of the diffusion equation in a semiconductor slab. These solutions are computed for Dirichlet null boundary conditions in the top and bottom planes of the slab and with a null internal electric field. The proposed model takes into account a finite diffusion length and an inclined trajectory. Such solutions may be used for radiation induced substrate diffusion currents modeling. View full abstract»

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Aims & Scope

IEEE Transactions on Nuclear Science focuses on all aspects of the theory and applications of nuclear science and engineering, including instrumentation for the detection and measurement of ionizing radiation; particle accelerators and their controls; nuclear medicine and its application; effects of radiation on materials, components, and systems; reactor instrumentation and controls; and measurement of radiation in space.

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