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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct. 2008

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Displaying Results 1 - 25 of 43
  • Table of contents

    Page(s): C1 - 2534
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    Freely Available from IEEE
  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (57 KB)  
    Freely Available from IEEE
  • Expanding the Editorial Board

    Page(s): 2535 - 2536
    Save to Project icon | Request Permissions | PDF file iconPDF (72 KB)  
    Freely Available from IEEE
  • Technology Circuit Co-Design for Ultra Fast InSb Quantum Well Transistors

    Page(s): 2537 - 2545
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1378 KB) |  | HTML iconHTML  

    Indium antimonide (InSb)-based quantum-well field- effect transistors (QWFETs) are conceived as a promising candidate for low-voltage high-performance applications. In this paper, we show complete technology-circuit assessment of InSb-based QWFETs. The codesign approach spans from the device/SPICE models, logic/memory circuit analysis, to technology requirements. We show the feasibility of the use of Si+InSb hybrid technology for future high-speed low-voltage applications. We prescribe the technology requirements as well as suggest the application space for InSb transistors. View full abstract»

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  • Lateral and Vertical Scaling of \hbox {In}_{0.7} \hbox {Ga}_{0.3}\hbox {As} HEMTs for Post-Si-CMOS Logic Applications

    Page(s): 2546 - 2553
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    In this paper, we have experimentally investigated the impact of lateral and vertical scaling of In0.7Ga0.3As high-electron-mobility transistors (HEMTs) onto their logic performance. We have found that reducing the In0.52Al0.48As insulator thickness results in much better electrostatic integrity and improved short-channel behavior down to a gate length of around 60 nm. Our nearly enhancement-mode 60-nm HEMTs feature VT = -0.02 V, DIBL = 93 mV/V, S = 88 mV/V, and ION/IOFF = 1.6 times104, at V DD = 0.5 V. We also estimate a gate delay of CV/I = 1.6 ps at VDD = 0.5 V. We have benchmarked these devices against state-of-the-art Si CMOS. For the same leakage current, which includes the gate leakage current, the InGaAs HEMTs exhibit 1.2times more current drive (ION) than the state-of-the-art 65-nm low-power CMOS technology at V DD = 0.5 V. View full abstract»

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  • Simulation of Life Testing Procedures for Estimating Long-Term Degradation and Lifetime of AlGaN/GaN HEMTs

    Page(s): 2554 - 2560
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB) |  | HTML iconHTML  

    Finite element 3-D thermal simulations of long-term degradation in AlGaN/GaN HEMTs for high-power applications are reported on, in which temperature evolves over time as the local degradation rate varies within the modeled device based on the local temperature of the degrading region (i.e., the channel). Specifically, hotter regions within a device are modeled as degrading faster due to a thermal component to the degradation rate equation. This allows self-consistent simulation of life testing, commonly used to estimate long-term reliability by extrapolating failure times seen at elevated channel temperatures to a lower "use" temperature. We find that it is necessary to consider the entire distribution of temperatures within the device instead of at one characteristic location to get the most accurate estimates for long-term device life. The effect of device geometry, assumed degradation mode, incorrect thermal resistance data, and dissipated power level on this lifetime estimation error is investigated. It is found that the error in the extrapolated failure time is greatly increased when both the thermal resistance is in error and the dissipated power of the life test does not match the expected power during operation, compared to when only one of these is off. View full abstract»

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  • Modeling of Short-Channel Effects in Organic Thin-Film Transistors

    Page(s): 2561 - 2567
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    We propose a model for short-channel organic thin-film transistors, which accounts for Poole-Frenkel field-dependent mobility and space-charge-limited current effects. The model is developed for devices operating in the linear regime, as well as in depletion and saturation regimes. Super linear output curves for low drain voltages, as well as nonsaturating currents, can be adequately described. Experimental results for short-channel P3HT devices have been fitted, showing good agreement with the proposed model. View full abstract»

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  • Tunable Capacitor Based on Polymer-Dispersed Liquid Crystal for Power Harvesting Microsystems

    Page(s): 2568 - 2573
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (722 KB) |  | HTML iconHTML  

    A tunable capacitor based on polymer-dispersed liquid-crystal (PDLC) technology is presented in this paper. Its application for robust power harvesting microsystems was investigated. The power harvesting device utilized a piezoelectric microcantilever excited by ambient random vibrations to convert mechanical energy into electric power. For improving the power harvesting efficiency, the PDLC tunable capacitor was used to adjust the resonance frequency of the piezoelectric microcantilever beam to match the frequency of the ambient vibrations in real time. The fabrication process and measurement results of the PDLC tunable capacitor are detailed. The measured tuning ratio of the PDLC tunable capacitor was 63% at 300-Hz excitation frequency when a 25-V driving voltage was applied. The dielectric and optical properties of the fabricated PDLC tunable capacitor have been examined thoroughly. Based on the results of the experiment, an equivalent lumped-element model of the PDLC tunable capacitor has been developed. The simulation results showed that the impedance of the developed model agreed well with that of the fabricated tunable capacitor. This model can be incorporated into the equivalent circuit of the integrated power harvesting system for efficiency optimization. View full abstract»

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  • Performance Modeling for Single- and Multiwall Carbon Nanotubes as Signal and Power Interconnects in Gigascale Systems

    Page(s): 2574 - 2582
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    Using physics-based circuit models, the performances of carbon nanotube (CNT) interconnects, both single- and multiwall (SWNT and MWNT), are benchmarked against their copper counterparts at a realistic operating temperature (100degC). The models used capture various electron phonon scattering mechanisms and the dependence of quantum conductance on temperature and diameter. It is demonstrated that any performance comparison between CNT and copper wires needs to be done at realistic temperatures because changes in temperature affect copper and CNT interconnects quite differently. The results of this paper demonstrate that a hybrid system of copper/SWNT/MWNT offers the highest performance enhancement for interconnects. View full abstract»

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  • Temperature Coefficient of Poly-Silicon TFT and its Application on Voltage Reference Circuit With Temperature Compensation in LTPS Process

    Page(s): 2583 - 2589
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    The temperature coefficient (TC) of n-type polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this paper. The relationship between the TC and the activation energy is observed and explained. From the experimental results, it is also found that TC is not sensitive to the deviation of the laser crystallization energy. On the contrary, channel width can effectively modulate the TC of TFTs. By using the diode-connected poly-Si TFTs with different channel widths, the first voltage reference circuit with temperature compensation for precise analog circuit design on glass substrate is proposed and realized. From the experimental results in a low-temperature poly-Si process, the output voltage of voltage reference circuit with temperature compensation exhibits a very low TC of 195 ppm/degC , between 25degC and 125degC. The proposed voltage reference circuit with temperature compensation can be applied to design precise analog circuits for system-on-panel or system-on-glass applications, which enables the analog circuits to be integrated in the active-matrix liquid crystal display panels. View full abstract»

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  • A Dual-Capture Wide Dynamic Range CMOS Image Sensor Using Floating-Diffusion Capacitor

    Page(s): 2590 - 2594
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (799 KB) |  | HTML iconHTML  

    A dual-capture wide dynamic range CMOS image sensor using an in-pixel floating-diffusion (FD) storage capacitor is proposed. The proposed structure uses the FD as a storage capacitor. The potential of the FD node is read out using a floating-gate capacitor without a contact metallization of the FD node to reduce the leakage. The proposed sensor was fabricated using a 0.35-mum CMOS process. The chip includes 320 times 240 pixels whose pitch is 5.6 mum and whose fill factor is 36%. The measurement results show 100-dB dynamic range, and the leakage at the non-metalized FD is reduced to about one-third of that of the conventional FD with the contact metallization. View full abstract»

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  • Negative Sustain Waveform for Improving Discharge Characteristics in AC Plasma Display Panel

    Page(s): 2595 - 2601
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    The discharge characteristics produced by a negative sustain waveform were examined in comparison with those produced by a positive sustain waveform. An image-intensified charge-coupled device (ICCD) revealed that the negative sustain waveform produced a faster and stronger sustain discharge than the positive sustain waveform. Simulation results also showed that the fast and strong sustain discharge produced by the negative sustain waveform was induced due to the rapid acceleration of the negative wall charges, such as electrons, when applying the negative sustain waveform directly to the electrode with negative wall charges, such as electrons. As a result, the luminance and luminous efficiency were both improved by about 14% and 13%, respectively, with a negative sustain pulse of -180 V when compared to the results with a positive sustain waveform of 180 V. View full abstract»

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  • TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture—Part I: Hot-Carrier-Reliability Evaluation

    Page(s): 2602 - 2613
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    This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping (NA), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern. View full abstract»

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  • Development of an Ultrafast On-the-Fly I_{\rm DLIN} Technique to Study NBTI in Plasma and Thermal Oxynitride p-MOSFETs

    Page(s): 2614 - 2622
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (751 KB) |  | HTML iconHTML  

    An ultrafast on-the-fly technique is developed to study linear drain current (I DLIN) degradation in plasma and thermal oxynitride p-MOSFETs during negative-bias temperature instability (NBTI) stress. The technique enhances the measurement resolution (ldquotime-zerordquo delay) down to 1 mus and helps to identify several key differences in NBTI behavior between plasma and thermal films. The impact of the time-zero delay on time, temperature, and bias dependence of NBTI is studied, and its influence on extrapolated safe-operating overdrive condition is analyzed. It is shown that plasma-nitrided films, in spite of having higher N density, are less susceptible to NBTI than their thermal counterparts. View full abstract»

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  • Semianalytical Modeling of Short-Channel Effects in Lightly Doped Silicon Trigate MOSFETs

    Page(s): 2623 - 2631
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (528 KB) |  | HTML iconHTML  

    A simple analytical expression of the 3-D potential distribution along the channel of lightly doped silicon trigate MOSFETs in weak inversion is derived, based on a perimeter-weighted approach of symmetric and asymmetric double-gate MOSFETs. The analytical solution is compared with the numerical solution of the 3-D Poisson's equation in the cases where the ratios of channel length/silicon thickness and channel length/channel width are ges 2. Good agreement is achieved at different positions within the channel. The perimeter-weighted approach fails at the corner regions of the silicon body; however, by using corner rounding and undoped channel to avoid corner effects in simulations, the agreement between model and simulation results is improved. By using the extra potential induced in the silicon film due to short-channel effects, the subthreshold drain current is determined in a semianalytical way, from which the subthreshold slope, the drain-induced barrier lowering, and the threshold voltage are extracted. View full abstract»

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  • Impact of Shear Strain and Quantum Confinement on  \langle \hbox {110}\rangle Channel nMOSFET With High-Stress CESL

    Page(s): 2632 - 2640
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    In this paper, we propose a new analytical electron mobility model in strained Si inversion layers suitable for implementation in a drift-diffusion simulator. Using our new model, a numerical study in conjunction with comprehensive bending experiments has demonstrated that (100)-Si has the optimum channel direction along <110> in terms of the device performance of strained 65-nm-node nMOSFETs with contact etch stop layer and that both the shear-strain component and the quantum confinement effect are key factors in contributing to this superiority. View full abstract»

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  • Determination of Work Functions in the \hbox {Ta}_{1 - x}\hbox {Al}_{x}\hbox {N}_{y}/\hbox {HfO}_{2} Advanced Gate Stack Using Combinatorial Methodology

    Page(s): 2641 - 2647
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    Combinatorial methodology enables the generation of comprehensive and consistent data sets, compared with the ldquoone-composition-at-a-timerdquo approach. We demonstrate, for the first time, the combinatorial methodology applied to the work function (Phim) extraction for Ta1-xAlxNy alloys as metal gates on HfO2, for complementary metal-oxide-semiconductor applications, by automated measurement of over 2000 capacitor devices. Scanning X-ray microdiffraction indicates that a solid solution exists for the Ta1-xAlxNy libraries for 0.05 les x les 0.50. The equivalent oxide thickness maps offer a snapshot of gate stack thermal stability, which show that Ta1-xAlxNy alloys are stable up to 950degC . The Phim of the Ta1-xAlxNy libraries can be tuned as a function of gate metal composition over a wide (0.05 les x les 0.50) composition range, as well as by annealing. We suggest that Ta0.9Al0.1N1.24 gate metal electrodes may be useful for p-channel metal-oxide-semiconductor applications. View full abstract»

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  • Effective Work Function Control With Aluminum Postdoping in the Ni Silicide/HfSiON Systems

    Page(s): 2648 - 2656
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    A simplified method of effective work function (Phieff) control to near the Si conduction band edge (Ec) was demonstrated in the Ni fully silicided (Ni-FUSI) gate/HfSiON system. The Phieff of NiSi (4.51 eV) decreased and saturated at 4.27 eV, owing to the use of an Al postdoping process, in which the implantation of Al ions into the upper part of the Ni silicide gate electrodes was followed by low-temperature drive-in annealing ( les 500degC) . There is no degradation of the gate leakage characteristics at the Ni-FUSI/HfSiON interface. The metallic state of piled-up Al just at the Ni-FUSI/HfSiON interface seems to be responsible for the Phieff near the vacuum work function of Al. The Al postdoping process simplifies a dual metal gate process, owing to single-step Al implantation for nMOS devices without complicated metal etching process for pMOS region. The physical mechanism of bidirectional Phieff modulation of Al pileup was also investigated. It was revealed that the opposite Phieff modulation, which is the increase in Phieff, occurs, owing to the formation of interfacial Al2O3 layer at the Ni-FUSI/SiO2 interface. Although the Al2O3 state also formed, it has little influence on the Phieff value at the Ni-FUSI/HfSiON interface. View full abstract»

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  • Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy

    Page(s): 2657 - 2664
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    Forward body biasing is a promising approach for realizing optimum threshold-voltage (V TH) scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias (VF) decreases the depletion width (X DEP) in the channel region, it reduces V TH rolloff significantly. MOSFET performance is maximized under forward body bias with steep retrograde channel doping, and such channel doping profiles are required to accomplish good short-channel behavior (small X DEP ) at low V TH notwithstanding body bias; therefore, the combination of forward body biasing with steep retrograde channel doping profile can extend the scaling limit of conventional bulk-Si CMOS technology to 10-nm gate length MOSFET. Considering forward biased p-n junction current, parasitic bipolar transistor, and CMOS latch-up phenomena, the upper limit for |VF| should be set at 0.6-0.7 V, which is sufficient to realize significant advantages of forward body biasing. View full abstract»

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  • A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETs

    Page(s): 2665 - 2677
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1021 KB) |  | HTML iconHTML  

    The performance of symmetric double-gate MOSFETs with dopant-segregated Schottky (DSS) source/drain (S/D) regions is investigated through a TCAD modeling study and compared to the performance of raised S/D (RSD) MOSFETs. It is shown that, while the doped extension region adjacent to the S/D Schottky barrier (SB) improves drive current by shrinking the SB, it is fundamentally limited by its dual role as a heavily doped S/D contact region to improve drive current and as a more lightly doped S/D extension region to reduce BTBT leakage. This restricts the design space for meeting low-standby-power leakage specifications, and so, the RSD structure ends up prevailing both in terms of leakage design space and on-state performance. For high-performance (HP) design, where the higher leakage specification permits heavier extension doping, the performances of optimized DSS and RSD MOSFETs are shown to be very similar. Thus, the optimal S/D design for HP is more likely to be decided by practical considerations such as process integration. View full abstract»

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  • Precise Modeling Framework for Short-Channel Double-Gate and Gate-All-Around MOSFETs

    Page(s): 2678 - 2686
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (561 KB) |  | HTML iconHTML  

    A precise modeling framework for short-channel nanoscale double-gate (DG) and gate-all-around (GAA) MOSFETs is presented. For the DG MOSFET, the modeling is based on a conformal mapping analysis of the potential distribution in the device body arising from the interelectrode capacitive coupling, combined with a self-consistent procedure to include the effects of the inversion charge. The DG interelectrode coupling, which dominates the subthreshold behavior of the device, can also be applied with a high degree of precision to the cylindrical GAA MOSFET by performing a simple geometric scaling transformation to account for the difference in gate control in the two devices. Near threshold, self-consistent procedures invoking Poisson's equation in combination with boundary conditions and suitable modeling expressions for the potential are applied to the two devices. In strong inversion, these solutions converge to those of the respective long-channel devices. The drain current is calculated as part of the self-consistent treatment. The results for both the electrostatics and the current are in excellent agreement with numerical simulations. View full abstract»

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  • Thickness Dependence of Hole Mobility in Ultrathin SiGe-Channel p-MOSFETs

    Page(s): 2687 - 2694
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1194 KB) |  | HTML iconHTML  

    A fundamental understanding of the mechanisms responsible for the dependence of hole mobility on SiGe channel layer thickness is presented for channel thicknesses down to 1.8 nm. This understanding is critical to the design of strained SiGe p-MOSFETs, as lattice mismatch limits the thickness of SiGe that can be grown on Si and as Ge outdiffusion during processing reduces the Ge fraction. Temperature-dependent measurements are used to extract the phonon-limited mobility as a function of SiGe channel thickness for strained Si0.57Ge0.43 heterostructures on bulk Si. The hole mobility is shown to degrade significantly for channel thickness below 4 nm due to a combination of phonon and interface scattering. Due to the finite nature of the quantum-well barrier, SiGe film thickness fluctuation scattering is not significant in this structure for channel thickness greater than 2.8 nm. View full abstract»

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  • Ultimate Accuracy for the nand Flash Program Algorithm Due to the Electron Injection Statistics

    Page(s): 2695 - 2702
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (267 KB) |  | HTML iconHTML  

    This paper investigates the ultimate accuracy of the NAND flash program algorithm that is determined by the statistical injection of electrons from the substrate to the floating gate. The granular nature of the electron flow during a constant-current Fowler-Nordheim program operation is shown to spread the programmed threshold-voltage distribution of the array cells. The electron injection statistics displays a Poissonian behavior for low amounts of transferred charge, but a sub-Poissonian character becomes clearly evident when large charge packets are stored. This effect is expected from the reduction of the tunnel oxide field that follows each electron storage event into the floating gate, establishing a correlation among such events. Finally, the impact of the electron injection statistical spread on the accuracy of the NAND flash program algorithm is investigated as a function of the technology node feature size, drawing projections on future NAND technologies. View full abstract»

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  • Gate Influence on the Layout Sensitivity of  \hbox {Si}_{1 - x}\hbox {Ge}_{x} \hbox {S/D} and \hbox {Si}_{1 - y}\hbox {C}_{y} \hbox {S/D} Transistors Including an Analytical Model

    Page(s): 2703 - 2711
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (646 KB) |  | HTML iconHTML  

    We present a simulation study on the effect of the gate module on the channel stress in Si1-xGex and Si1-yCy S/D MOS transistors. Stiff gate materials, such as titanium nitride, lead to a decreased channel stress, while a replacement-gate scheme allows the increase of the effectiveness of the Si1-xGex and Si1-yCy S/D techniques significantly, independent of the gate material used. The drawback of using a replacement gate is that the channel stress becomes more sensitive to layout variations. In terms of effect on Si1-xGex/Si1-yCy S/D stress generation, using a thin metal gate capped by polysilicon is similar to a full metal gate if the thin metal gate thickness exceeds 10 nm. Even metal gates as thin as 1 nm have a clear influence on the stress generation by Si1-xGex/Si1-yCy S/D. Removing and redepositing the polysilicon layer while leaving the underlying metal gate unchanged increases the stress, although not to the same extent as for complete gate removal. A simple analytical model that estimates the stress in nested short-channel Si1-xGex and Si1-yCy S/D transistors is presented. This model includes the effect of germanium/carbon concentration, active-area length, as well as the effect of gate length and the Young's modulus of the gate. Good qualitative agreement with 2-D finite element modeling is demonstrated. View full abstract»

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  • Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

    Page(s): 2712 - 2717
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (587 KB) |  | HTML iconHTML  

    Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly Cgb, becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (Idsat) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (gm) degradation and, eventually, cutoff frequency (fT) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. fT is largely affected by local stress change, i.e., gm degradation at minimal gate poly (GP) pitch and gate-to-active spacing, fT is dominated by increased parasitic capacitance (Cgb) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in fT has been observed through layout optimization for Cgb reduction by increasing the transistor active-to-SC spacing. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology