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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 10 • Date Oct. 2008

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  • Table of contents

    Publication Year: 2008, Page(s): C1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2008, Page(s): C2
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  • Guest Editorial Special Section on Application Specific Processors

    Publication Year: 2008, Page(s):1257 - 1258
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  • Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors

    Publication Year: 2008, Page(s):1259 - 1267
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (959 KB) | HTML iconHTML

    Automatic generation of a customized instruction set, starting from an input application code, is a complex problem that has received considerable attention in the past few years. Because of its complexity, only simplified versions of the problem have been solved exactly so far. For example, exact algorithms have been proposed for custom instruction identification but that do not consider recurren... View full abstract»

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  • Outer Loop Pipelining for Application Specific Datapaths in FPGAs

    Publication Year: 2008, Page(s):1268 - 1280
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (978 KB) | HTML iconHTML

    Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we extend and adapt an existing outer loop pipelining approach known as single dimension software pipelining to generate schedules for field-programmable gate-array (FPGA) hardware coprocessors. Each loop level in nine test loop... View full abstract»

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  • A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors

    Publication Year: 2008, Page(s):1281 - 1294
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (889 KB) | HTML iconHTML

    During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable application-specific instruction set processors (rASIPs) which combine a programmable base processor with a reconfigurable fabric. Although such processors promise to deliver excellent balance between performance and flexibilit... View full abstract»

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  • Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation

    Publication Year: 2008, Page(s):1295 - 1308
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3922 KB) | HTML iconHTML

    State-of-the-art application-specific instruction set processors (ASIPs) allow the designer to define individual prefabrication customizations, thus improving the degree of specialization towards the actual application requirements, e.g., the computational hot spots. However, only a subset of hot spots can be targeted to keep the ASIP within a reasonable size. We propose a modular special instruct... View full abstract»

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  • A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment

    Publication Year: 2008, Page(s):1309 - 1320
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2696 KB) | HTML iconHTML

    Future mobile and wireless communication networks require flexible modem architectures to support seamless services between different network standards. Hence, a common hardware platform that can support multiple protocols implemented or controlled by software, generally referred to as software defined radio (SDR), is essential. This paper presents a family of dynamically reconfigurable applicatio... View full abstract»

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  • High Performance Architecture of an Application Specific Processor for the H.264 Deblocking Filter

    Publication Year: 2008, Page(s):1321 - 1334
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB) | HTML iconHTML

    This paper presents an efficient architecture of an application specific processor (ASP) designed for the deblocking filter algorithm of the H.264 video compression standard. Several optimization techniques at different design levels, such as vector register, pipeline processing, very long instruction word (VLIW) processor, and predication, are utilized in this design. The proposed ASP can meet th... View full abstract»

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  • A Processing Path Dispatcher in Network Processor MPSoCs

    Publication Year: 2008, Page(s):1335 - 1345
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1948 KB) | HTML iconHTML

    Multi-field packet classification problems discussed in the literature are typically constrained to the Internet five-tuple and primarily address the problem of network quality-of-service (QoS) support and access control. In this paper, we present a solution for a classification problem that is used for optimized packet assignment to different data paths within a network processor system-on-chip (... View full abstract»

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  • Automatic Processor Customization for Zero-Overhead Online Software Verification

    Publication Year: 2008, Page(s):1346 - 1357
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (551 KB) | HTML iconHTML

    The PSL-to-Verilog (P2V) compiler can translate a set of assertions about a block-structured software program into a hardware design to be executed concurrently with the program. The assertions validate the correctness of the software program without altering the program's temporal behavior in any way, a result never previously achieved by any online model-checking system. Additionally, the techni... View full abstract»

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  • Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel

    Publication Year: 2008, Page(s):1358 - 1371
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3007 KB) | HTML iconHTML

    To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo decoder is proposed. In this paper, we systematically analyze the timing charts of both the Viterbi algorithm and the MAP algorithm. Then, three techniques, including Distribution, Pointer, and Parallel schemes, are introd... View full abstract»

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  • A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems

    Publication Year: 2008, Page(s):1372 - 1384
    Cited by:  Papers (4)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (928 KB) | HTML iconHTML

    In this paper, we propose some soft-error-tolerant latches and flip-flops that can be used in dual-VDD systems. By utilizing local redundancy and inner feedback techniques, the latches and flip-flops can recover from soft errors caused by cosmic rays and particle strikes. The proposed flip-flop can be used as a level shifter without the problems of static leakage and redundant switching activity. ... View full abstract»

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  • Efficient Hierarchical Motion Estimation Algorithm and Its VLSI Architecture

    Publication Year: 2008, Page(s):1385 - 1398
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3211 KB) | HTML iconHTML

    This paper addresses the development and hardware implementation of an efficient hierarchical motion estimation algorithm, HMEA, using multiresolution frames to reduce the computational complexity. Excellent estimation performance is ensured using an averaging filter to downsample the original image. At the smallest resolution, the least two motion vector candidates are selected using a full-searc... View full abstract»

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  • Error-Resilient Motion Estimation Architecture

    Publication Year: 2008, Page(s):1399 - 1412
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4571 KB) | HTML iconHTML

    In this paper, we propose an energy-efficient motion estimation architecture. The proposed architecture employs the principle of error-resiliency to combat logic level timing errors that may arise in average-case designs in presence of process variations and/or due to overscaling of the supply voltage [voltage overscaling (VOS)] and thereby achieves power reduction. Error-resiliency is incorporate... View full abstract»

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  • Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication

    Publication Year: 2008, Page(s):1413 - 1426
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1340 KB) | HTML iconHTML

    The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose Flexbus, a new architecture th... View full abstract»

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    Publication Year: 2008, Page(s): 1427
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    Publication Year: 2008, Page(s): 1428
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2008, Page(s): C3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors

    Publication Year: 2008, Page(s): C4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu