# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 30

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2008, Page(s): C2
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• ### Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC

Publication Year: 2008, Page(s):2157 - 2165
Cited by:  Papers (12)
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The ever-shrinking CMOS technology favors digital circuitry but imposes a challenge to the analog designer faced with limitations such as process gradients and random device variations. However, the trend to greater integration and systems-on- chips (SoCs), requires that digital and analog blocks be merged into single chips. High resolution digital-analog converters (DACs) are especially sensitive... View full abstract»

• ### A 16-bit 65-MS/s Pipeline ADC With 80-dBFS SNR Using Analog Auto-Calibration in SiGe SOI Complementary BiCMOS

Publication Year: 2008, Page(s):2166 - 2177
Cited by:  Papers (10)
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A 16-bit 65-MS/s switched-capacitors pipeline analog-to-digital converter built in 0.45-mum 25-GHz fT complementary silicon-on-insulator BiCMOS delivers 80.1-dBFS signal-to-noise ratio, 98-dBc spurious-free dynamic range (SFDR) with 3-Vpp input range at 2-MHz input frequency. The 5 times 5.3 mm2 die consumes 1.7 W from a dual plusmn2.7-V supply. A noniterative analog auto-cal... View full abstract»

• ### A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational, 100-MS/s, MOS SHA

Publication Year: 2008, Page(s):2178 - 2187
Cited by:  Papers (7)
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This paper proposes a circuit to linearize the signal current and improve the distortion characteristics at the input of a current-mode circuit. Input voltage-to-current (V/I) conversion is carried out by a resistor that connects the signal source and the current input terminal of the current-mode circuit. The signal current flowing into the current-mode circuit through this resistor is distorted ... View full abstract»

• ### Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps

Publication Year: 2008, Page(s):2188 - 2201
Cited by:  Papers (2)
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This paper presents several comprehensive and novel circuit techniques that can be efficiently applied to low-voltage (LV) high-speed reset-opamp (RO) and switched-opamp (SO) in LV switched-capacitor circuits. The first, designated as virtual-ground common-mode (CM) feedback with output CM error correction, allows the design of fully differential RO circuits that could only be traditionally implem... View full abstract»

• ### Wire Optimization for Multimedia SoC and SiP Designs

Publication Year: 2008, Page(s):2202 - 2215
Cited by:  Papers (8)
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With advances in VLSI integration technology, a large number of hardware components can be integrated into a single chip. To provide the communication bandwidth for these components, existing bus-based interconnects often suffer from a large area occupied by a large number of bus signals. To address this issue, this paper proposes a new protocol for on-chip or in-package communication that is term... View full abstract»

• ### Low-Complexity Binary Morphology Architectures With Flat Rectangular Structuring Elements

Publication Year: 2008, Page(s):2216 - 2225
Cited by:  Papers (10)
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This article describes and evaluates algorithms and their hardware architectures for binary morphological erosion and dilation. In particular, a fast stall-free low-complexity architecture is proposed that takes advantage of the morphological duality principle and structuring element (SE) decomposition. The design is intended to be used as a hardware accelerator in real-time embedded processing ap... View full abstract»

• ### A Novel DCXO Module for Clock Synchronization in MPEG2 Transport System

Publication Year: 2008, Page(s):2226 - 2237
Cited by:  Papers (15)  |  Patents (2)
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This paper presents a unique on-chip digital control crystal oscillator (DCXO) module that is used for clock synchronization in MPEG2 data transport system. This module is built inside a phase-locked loop (PLL) and is achieved through flying-adder frequency synthesis architecture. It is designed at 27 MHz with a tuning range of plusmn10 kHz. The linearity at the range of 27 MHz plusmn10 kHz is mea... View full abstract»

• ### Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits

Publication Year: 2008, Page(s):2238 - 2248
Cited by:  Papers (9)
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In deep-submicrometer technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis of the entire die. This ... View full abstract»

• ### Energy, Performance, and Probability Tradeoffs for Energy-Efficient Probabilistic CMOS Circuits

Publication Year: 2008, Page(s):2249 - 2262
Cited by:  Papers (26)
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The scaling trend of semiconductor devices has raised several issues such as energy consumption and heat dissipation, as well as the increasing probabilistic behavior of devices. Motivated by the necessity to consider probabilistic approaches to future designs, probabilistic CMOS (PCMOS) based computing has been proposed. PCMOS devices are inherently probabilistic devices that compute correctly wi... View full abstract»

• ### A Clock-Less Jitter Spectral Analysis Technique

Publication Year: 2008, Page(s):2263 - 2272
Cited by:  Papers (1)
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In this paper, we propose a method for extracting the spectral information of a multigigahertz jittery signal without using an ideal reference clock. This method utilizes existing on-chip single-shot period measurement techniques to measure single periods of a multigigahertz signal for analysis. Utilizing the same sampling and measuring principle, we propose another less computationally intensive ... View full abstract»

• ### Reconstruction of Nonuniformly Sampled Bandlimited Signals Using a Differentiator–Multiplier Cascade

Publication Year: 2008, Page(s):2273 - 2286
Cited by:  Papers (55)
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This paper considers the problem of reconstructing a bandlimited signal from its nonuniform samples. Based on a discrete-time equivalent model for nonuniform sampling, we propose the differentiator-multiplier cascade, a multistage reconstruction system that recovers the uniform samples from the nonuniform samples. Rather than using optimally designed reconstruction filters, the system improves the... View full abstract»

• ### On the Polyphase Decomposition for Design of Generalized Comb Decimation Filters

Publication Year: 2008, Page(s):2287 - 2299
Cited by:  Papers (14)
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Generalized comb filters (GCFs) are efficient anti-aliasing decimation filters with improved selectivity and quantization noise (QN) rejection performance around the so called folding bands with respect to classical comb filters. In this paper, we address the design of GCF filters by proposing an efficient partial polyphase architecture with the aim to reduce the data rate as much as possible afte... View full abstract»

• ### Digital IIR Integrator Design Using Richardson Extrapolation and Fractional Delay

Publication Year: 2008, Page(s):2300 - 2309
Cited by:  Papers (18)
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In this paper, a new design of digital integrator is investigated. First, the trapezoidal integration rule and differential equation are applied to derive the transfer function of the digital integrator. The Richardson extrapolation is then used to generate high-accuracy results while using low-order formulas. Next, the conventional Lagrange finite-impulse response fractional delay filter is direc... View full abstract»

• ### Information Theoretic Approach to Complexity Reduction of FIR Filter Design

Publication Year: 2008, Page(s):2310 - 2321
Cited by:  Papers (29)
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This paper presents a new paradigm of design methodology to reduce the complexity of application-specific finite-impulse response (FIR) digital filters. A new adder graph data structure called the multiroot binary partition graph (MBPG) is proposed for the formulation of the multiple constant multiplication problem of FIR filter design. The set of coefficients in any fixed point representation is ... View full abstract»

• ### A Lattice Structure of Biorthogonal Linear-Phase Filter Banks With Higher Order Feasible Building Blocks

Publication Year: 2008, Page(s):2322 - 2331
Cited by:  Papers (9)
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This paper proposes a lattice structure of biorthogonal linear-phase filter banks (BOLPFBs) using new building blocks which can obtain long filters with fewer number of building blocks than conventional ones. The structure is derived from a generalization of the building blocks of first-order LPFBs. Furthermore, the proposed building blocks are applicable for both even and odd number of channels. ... View full abstract»

• ### Ultrafast analog Fourier transform using 2-D LC lattice

Publication Year: 2008, Page(s):2332 - 2343
Cited by:  Papers (15)  |  Patents (2)
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We describe how a 2-D rectangular lattice of inductors and capacitors can serve as an analog Fourier transform device, generating an approximate discrete Fourier transform (DFT) of an arbitrary input vector of fixed length. The lattice displays diffractive and refractive effects and mimics the combined optical effects of a thin-slit aperture and lens. Diffraction theories in optics are usually der... View full abstract»

• ### Blind-Channel Estimation for MIMO Systems With Structured Transmit Delay Scheme

Publication Year: 2008, Page(s):2344 - 2355
Cited by:  Papers (3)
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This paper considers blind-channel estimation for multiple-input multiple-output (MIMO) systems with structured transmitter design. First, a structured transmit delay (STD) scheme is proposed for MIMO systems. Unlike existing transmit diversity approaches, in which different antennas transmit delayed, zero padded, or time-reversed versions of the same signal, in the proposed scheme, each antenna t... View full abstract»

• ### Nonnegative Matrix Factorization Applied to Nonlinear Speech and Image Cryptosystems

Publication Year: 2008, Page(s):2356 - 2367
Cited by:  Papers (10)
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Nonnegative matrix factorization (NMF) is widely used in signal separation and image compression. Motivated by its successful applications, we propose a new cryptosystem based on NMF, where the nonlinear mixing (NLM) model with a strong noise is introduced for encryption and NMF is used for decryption. The security of the cryptosystem relies on following two facts: 1) the constructed multivariable... View full abstract»

• ### Quantum-Noise Limited Distance Resolution of Optical Range Imaging Techniques

Publication Year: 2008, Page(s):2368 - 2377
Cited by:  Papers (15)
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The most common optical distance imaging methods (triangulation, interferometry and time-of-flight ranging) can all be described in a unified way as linear shift-invariant systems in which the determination of distance corresponds to the measurement of a spatial or temporal phase. Since the ultimate precision of such a phase measurement is limited by quantum noise of the involved photons or photoc... View full abstract»

• ### Subgradient-Based Neural Networks for Nonsmooth Convex Optimization Problems

Publication Year: 2008, Page(s):2378 - 2391
Cited by:  Papers (40)
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This paper develops a neural network for solving the general nonsmooth convex optimization problems. The proposed neural network is modeled by a differential inclusion. Compared with the existing neural networks for solving nonsmooth convex optimization problems, this neural network has a wider domain for implementation. Under a suitable assumption on the constraint set, it is proved that for a gi... View full abstract»

• ### Two-parameter discontinuity-induced bifurcation curves in a ZAD-strategy-controlled dc-dc buck converter

Publication Year: 2008, Page(s):2392 - 2401
Cited by:  Papers (16)
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The dynamics of a zero-average dynamic strategy controlled dc-dc Buck converter, modelled by a set of differential equations with discontinuous right-hand side is studied. Period-doubling and corner-collision bifurcations are found to occur close to each other under small parameter variations. Closer examination of the parameter space leads to the discovery of a novel bifurcation. This type of bif... View full abstract»

• ### Optimal Synthesis of State-Estimate Feedback Controllers With Minimum $l_{2}$-Sensitivity

Publication Year: 2008, Page(s):2402 - 2410
Cited by:  Papers (2)
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This paper investigates the problem of synthesizing the optimal structure of a state-estimate feedback controller with minimum l 2-sensitivity and no overflow. First, the l 2-sensitivity of a closed-loop transfer function with respect to the coefficients of a state-estimate feedback controller is analyzed. Next, two iterative techniques for obtaining the coordin... View full abstract»

• ### Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints

Publication Year: 2008, Page(s):2411 - 2422
Cited by:  Papers (9)
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This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis data... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK