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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 10 • Date Oct. 2008

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Displaying Results 1 - 22 of 22
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Page(s): C2
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  • Multiprocessor System-on-Chip (MPSoC) Technology

    Page(s): 1701 - 1713
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    The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. A wide range of MPSoC architectures have been developed over the past decade. This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture. We consider some of the technological trends that have driven the design of MPSoCs. We also survey computer-aided design problems relevant to the design of MPSoCs. View full abstract»

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  • A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips

    Page(s): 1714 - 1724
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    In this paper, we propose a high-performance droplet router for a digital microfluidic biochip (DMFB) design. Due to recent advancements in the biomicro electromechanical system and its various applications to clinical, environmental, and military operations, the design complexity and the scale of a DMFB are expected to explode in the near future, thus requiring strong support from CAD as in conventional VLSI design. Among the multiple design stages of a DMFB, droplet routing, which schedules the movement of each droplet in a time-multiplexed manner, is one of the most critical design challenges due to high complexity as well as large impacts on performance. Our algorithm first routes a droplet with higher by passibility which is less likely to block the movement of the others. When multiple droplets form a deadlock, our algorithm resolves it by backing off some droplets for concession. The final compaction step further enhances timing as well as fault tolerance by tuning each droplet movement greedily. The experimental results on hard benchmarks show that our algorithm achieves over 35 x and 20 x better routability with comparable timing and fault tolerance than the popular prioritized A* search and the state-of-the-art network-flow-based algorithm, respectively. View full abstract»

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  • Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits

    Page(s): 1725 - 1736
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2483 KB) |  | HTML iconHTML  

    Carbon-nanotube (CNT) field-effect transistors (CNFETs) are promising extensions to silicon CMOS. Simulations show that CNFET inverters fabricated with a perfect CNFET technology have 13 times better energy delay product compared with 32-nm silicon CMOS inverters. The following two fundamental challenges prevent the fabrication of CNFET circuits with the aforementioned advantages: 1) misaligned and mispositioned CNTs and 2) metallic CNTs. Misaligned and mispositioned CNTs can cause incorrect functionality. This paper presents a technique for designing arbitrary logic functions using CNFET circuits that are guaranteed to implement correct functions even in the presence of a large number of misaligned and mispositioned CNTs. Experimental demonstration of misaligned and mispositioned CNT-immune logic structures is also presented. View full abstract»

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  • Symbolic Compilation of PSL

    Page(s): 1737 - 1750
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    The IEEE standard property specification language (PSL) is increasingly used in many phases of the hardware design cycle, from specification to verification. PSL combines linear temporal logic (LTL) with sequential extended regular expressions (SEREs) and, thus, provides a natural formalism to express all omega-regular properties. In this paper, we propose a new method for efficiently converting PSL formulas into symbolically represented nondeterministic (generalized) Buchi automata (NGBA) that are typically used in many verification and analysis tools. The construction is based on a normal form that separates the LTL and the SERE components, and allows for a modular and specialized encoding. The compilation is enhanced by a set of syntactic transformations that aim at reducing the state space of the resulting NGBA. These rules enable to achieve, at low cost, the simplification that can be achieved with expensive semantic techniques based on minimization. A thorough experimental analysis over large sets of paradigmatic properties (from patterns of properties commonly used in practice) shows that our approach drastically reduces the compilation time and positively affects the overall search time. View full abstract»

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  • Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs

    Page(s): 1751 - 1760
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (731 KB) |  | HTML iconHTML  

    Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of field-programmable gate arrays (FPGAs). Boolean satisfiability (SAT)-based Boolean matching (SAT-BM) has been proposed, but computational complexity prohibits its practical deployment. In this paper, we leverage symmetries present in both Boolean functions and target FPGA architectures to prune the solution space, and we also propose some techniques to reduce the replication runtime for SAT instance generation using the incremental SAT reasoning engine. Experiment shows that our SAT-BM reduces runtime by 226times compared with the original SAT-BM algorithm, making SAT-BM more practical. View full abstract»

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  • Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits

    Page(s): 1761 - 1774
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    The increasing importance of datapath circuits in complex systems-on-chip calls for special arithmetic optimizations. The goal is to automatically achieve the handcrafted results which escape classic logic optimizations. Some work has been done in the recent years to infer the use of the carry-save representation in the synthesis of arithmetic circuits. Yet, many cases of practical interest cannot be handled due to the scattering of logic operations among the arithmetic ones - particularly in arithmetic computations which are originally described at the bit level in high-level languages such as C. We therefore introduce an algorithm to restructure dataflow graphs so that they can be synthesized as high-quality arithmetic circuits, close to those that an expert designer would conceive. On typical embedded software benchmarks which could be advantageously implemented with hardware accelerators, our technique always reduces tangibly the critical path by up to 46% and generally achieves the quality of manual implementations. In many cases, our algorithm also manages to reduce the cell area by up to 10%-20%. View full abstract»

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  • Transforming Cyclic Circuits Into Acyclic Equivalents

    Page(s): 1775 - 1787
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    Designers and high-level synthesis tools can introduce unwanted cycles in digital circuits, and for certain combinational functions, cyclic circuits that are stable and do not hold state are the smallest or most natural representations. Cyclic combinational circuits have well-defined functional behavior yet wreak havoc with most logic synthesis and timing tools, which require combinational logic to be acyclic. As such, some sort of cycle-removal step is necessary to handle these circuits with existing tools. We present a two-stage algorithm for transforming a combinational cyclic circuit into an equivalent acyclic circuit. The first part quickly and exactly characterizes all combinational behavior of a cyclic circuit. It starts by applying input patterns to each input and examining the boundary between gates whose outputs are and are not defined to find additional input patterns that make the circuit behave combinationally. It produces sets of assignments to inputs that together cover all combinational behavior. This can be used to report errors, as an optimization aid, or to restructure the circuit into an acyclic equivalent. The second stage of our algorithm does this restructuring by creating an acyclic circuit fragment from each of these assignments and assembles these fragments into an acyclic circuit that reproduces all the combinational behavior of the original cyclic circuit. Experiments show that our algorithm runs in seconds on real-life cyclic circuits, making it useful in practice. View full abstract»

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  • General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing

    Page(s): 1788 - 1797
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (602 KB) |  | HTML iconHTML  

    Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft-error rates caused by single-event upsets (SEUs) is becoming exponentially greater. As a consequence of technology feature size reduction, the SEU rate for typical microprocessor logic at sea level will go from one in hundred years to one every minute. Unfortunately, the gate sizing requirements of power reduction and resiliency against SEU can be contradictory. 1) We consider the effects of gate sizing on SEU and incorporate the relationship between power reduction and SEU resiliency to develop a new method for power optimization under SEU constraints. 2) Although a nonlinear programming approach is a more obvious solution, we propose a convex programming formulation that can be solved efficiently. 3) Many of the optimal existing techniques for gate sizing deal with an exponential number of paths in the circuit. We prove that it is sufficient to consider a linear number of constraints. 4) We generalize our methodology to include nonlinear delay models and leakage power as well. As an important preprocessing step, we apply statistical modeling and validation techniques to quantify the impact of fault masking on the SEU rate. Furthermore, we adapt our method to incorporate process variation and evaluate our gate sizing technique under uncertainty. We evaluate the effectiveness of our methodology on ISCAS benchmarks and show that error rates can be reduced by a factor of 100%-200% while, on average, the power reduction is simultaneously decreased by less than 6%-10%, respectively, compared to the optimal power saving with no error rate constraints. View full abstract»

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  • Charge Recycling in Power-Gated CMOS Circuits

    Page(s): 1798 - 1811
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    The design of a suitable power gating (e.g., multithreshold or super cutoff CMOS) structure is an important and challenging task in sub-90-nm very large scale integration (VLSI) circuits where leakage currents are significant. In designs where the mode transitions are frequent, a significant amount of energy is consumed to turn on or off the power gating structure. It is thus desirable to develop a power gating solution that minimizes the energy consumed during mode transitions. This paper presents such a solution by recycling charge between the virtual power and ground rails immediately after entering the sleep mode and just before wakeup. The proposed method can save up to 43% of the dynamic energy wasted during mode transition while maintaining the wakeup time of the original circuit. It also reduces the peak negative voltage value and the settling time of the ground bounce. View full abstract»

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  • A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations

    Page(s): 1812 - 1825
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    In this paper, we present a unified approach for the statistical timing and leakage analysis of circuits in the presence of intradie variations. The intradie variations in device parameters are modeled as a spatial stochastic process with a given covariance function. The covariance function is used to construct a Karhunen-Loeve expansion of the spatial process. This leads to representing the various parameters of all components on the chip in terms of a common set of abstract random variables. The leakage and propagation delay of each gate are represented as quadratic polynomials (QPs), which are elements of a vector space whose bases are multivariate quadratic orthogonal polynomials of the device parameters. In the case of signal arrival times, we describe an efficient method to propagate the QPs through the circuit to obtain a QP representation of the signal arrival times at the primary outputs. The analysis is extended to include sequential components so that flip-flop parameters and clock arrival times can be treated as random variables. This allows efficient estimation of the timing yield of the circuit. We show how a similar representation of QP can be used to model leakage of gates and develop an efficient method to compute a QP representation of the total chip leakage. The proposed techniques and quadratic models were exercised on ISCAS89 benchmark circuits and compared with Monte Carlo (MC) simulations. The results show that the techniques are very accurate and several orders of magnitude faster than MC simulation. View full abstract»

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  • Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models

    Page(s): 1826 - 1839
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    Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timing verification, such as the use of process corners and predefined timing margins, cannot readily handle within-die variations. Recently, statistical static timing analysis (SSTA) has been proposed as a way to deal with variability. Although many powerful techniques have been proposed, the fact that SSTA requires a significant change of methodology has delayed its wide adoption. In this paper, we propose a framework whereby the familiar concepts of corners and margins, which are generally meaningful at the transistor or cell level, are elevated to the chip level in order to handle within-die variations. This is achieved by using high-level models, such as the generic path model or the generic circuit model with different classes of paths, to represent the behavior of typical designs. These models allow us to determine ldquoyield-specificrdquo margins (setup and hold margins) and virtual corners, which, if applied during standard (deterministic) timing analysis, would guarantee the desired yield. Our framework can be used at an early stage of circuit design and is consistent with traditional timing verification methodology. View full abstract»

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  • Rapid Detailed Temperature Estimation for Highly Coupled IC Interconnect

    Page(s): 1840 - 1851
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    Steady-state temperature due to Joule self-heating for highly coupled integrated-circuit interconnect can be found rapidly on individual interconnect segments during electromigration reliability verification. It has previously been shown that the dc electric current solution on each interconnect segment of a net may be modified to form the analytical solution of the 1-D time-independent heat equation along the entire net. A symbolic solution of the network equations (requiring O(P3) operations, where P is the number of nodes) is first evaluated to solve the electrical problem and then evaluated again to solve the resulting Joule heat problem (each evaluation requiring O(P) operations). The symbolic solution is extended here to couple each interconnect segment to the weighted average temperature of the segments on neighboring nets. The temperature over the entire set of nets may be found by iterating until convergence, which does not require a significant overall increase in operations. The accuracy of the temperature trajectories is principally dependent on the validity of the assumptions that the temperature background seen by each individual interconnect segment is uniform and that vias conduct heat only along their lengths. The estimated temperature of self-heated nets is 110% of the finite-element result for a realistic layout example. The net-based solution is well suited to distributed processing and identifying problematic layout. View full abstract»

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  • Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty

    Page(s): 1852 - 1865
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    Due to the hard-to-measure distributions of real process data, it is difficult to provide accurate parametric yield prediction for modern circuit design. Most existing approaches are not able to handle the uncertain distribution properties coming from the process data. Other approaches are inadequate in considering correlations among the distributions of variations. This paper suggests a new approach that not only takes care of correlations among distributions but also provides a low-cost and efficient computation scheme. The proposed method approximates the parameter variations with Chebyshev affine arithmetic (CAA) to capture both the uncertainty and nonlinearity in a cumulative distribution function. The CAA-based probabilistic range presentation describes, both fully and partially, specified process and environmental parameters. Thus, we are able to predict the probability bounds for leakage consumption with unknown dependences among variations. The end result is the chip-level parametric yield estimation based on leakage prediction. Experimental results demonstrate that the new approach provides a reliable bound estimation, which leads to a 20% yield improvement compared with only using the intervals of partially specified uncertainties. View full abstract»

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  • Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels

    Page(s): 1866 - 1879
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    Achieving effective run-time mapping on multiprocessor systems-on-chip (MPSoCs) is a challenging task, particularly since the arrival order of the target applications is not known a priori. This paper targets real-time applications which are dynamically mapped onto embedded MPSoCs, where communication happens via the Network-on-Chip (NoC) approach, and resources connected to the NoC have multiple voltage levels. We address precisely the energy- and performance-aware incremental mapping problem for NoCs with multiple voltage levels and propose an efficient technique (consisting of region selection and node allocation) to solve it. Moreover, the proposed technique allows for new applications to be added to the system with minimal in- terprocessor communication overhead. Experimental results show that the proposed technique is very fast, and as much as 50% communication energy savings can be achieved compared to using an arbitrary allocation scheme. View full abstract»

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  • Statistical Static Timing Analysis Considering Process Variation Model Uncertainty

    Page(s): 1880 - 1890
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    Increasing variability in modern manufacturing processes makes it important to predict the yields of chip designs at early design stage. In recent years, a number of statistical static timing analysis (SSTA) and statistical circuit optimization techniques have emerged to quickly estimate the design yield and perform robust optimization. These statistical methods often rely on the availability of statistical process variation models whose accuracy, however, is severely hampered by the limitations in test structure design, test time, and various sources of inaccuracy inevitably incurred in process characterization. To consider model characterization inaccuracy, we present an efficient importance sampling based optimization framework that can translate the uncertainty in process models to the uncertainty in circuit performance, thus offering the desired statistical best/worst case circuit analysis capability accounting for the unavoidable complexity in process characterization. Furthermore, our new technique provides valuable guidance to process characterization. Examples are included to demonstrate the application of our general analysis framework under the context of SSTA. View full abstract»

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  • Design-Specific Optimization Considering Supply and Threshold Voltage Variations

    Page(s): 1891 - 1901
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    Variations in supply (V dd) and threshold voltages (V th) significantly impact parametric yield. These variations also affect V dd and V th scaling, two power reduction techniques that effectively reduce dynamic and static power consumption. This paper presents a statistical methodology for maximizing yield and optimizing supply and threshold voltage scaling under the V dd and V th variations. A design-specific feasible region is constrained by a minimum performance and maximum temperature in the V th - V dd plane. A tolerance box is placed in the feasible region so that its center provides the nominal values for V dd and V th such that the design has a maximum immunity to the variations and maximizes the yield for the given constraints. It is demonstrated that the location of the tolerance box and, therefore, the values of V dd and V th depend on the design metrics, circuit switching activity, transistor sizing, and the given constraints. Monte Carlo simulations indicate a 25% increase in the yield for 90-nm CMOS technology. In addition, the methodology can be adopted as a variability-aware guideline in a design specific power and performance optimization and is applicable to both continuous and discrete voltage scaling. SPECTRE simulations verify the developed method. View full abstract»

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    Page(s): 1902
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    Page(s): 1903
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    Page(s): 1904
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    Page(s): C3
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu