By Topic

# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 25 of 32

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2008, Page(s): C2
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• ### An Automatic Antenna Tuning System Using Only RF Signal Amplitudes

Publication Year: 2008, Page(s):833 - 837
Cited by:  Papers (21)  |  Patents (9)
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The operating environment of mobile phones fluctuates continuously, due to changing handling conditions and nearby objects. The resulting fluctuations in antenna impedance cause both a decrease in link quality and a higher standing wave ratio, that requires more robust and hence less efficient power amplifier implementations. In this paper, an automatic antenna tuner system for handheld applicatio... View full abstract»

• ### Design Technique for Mitigation of Soft Errors in Differential Switched-Capacitor Circuits

Publication Year: 2008, Page(s):838 - 842
Cited by:  Papers (18)
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The floating amplifier inputs in switched-capacitor differential circuits are identified as extremely vulnerable to single events. A radiation hardened by design mitigation technique is presented. The vulnerability of the floating inputs is improved by an order of magnitude with negligible penalties in area, power, speed and noise performance. View full abstract»

• ### Optimal Filter Networks

Publication Year: 2008, Page(s):843 - 847
Cited by:  Papers (3)
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Filters with optimal dynamic range may be generated through state transformation. Examples show that this optimization leads to a chip-area and power-consumption reduction up to 50%. The method is flexible enough to apply to any filter transfer function and any method to determine the dynamic range. It also allows control over the complexity of the resulting optimal filters. View full abstract»

• ### Delay Estimation in the Presence of Timing Noise

Publication Year: 2008, Page(s):848 - 852
Cited by:  Papers (2)
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We consider the problem of delay estimation in the presence of timing noise. We introduce an iterative algorithm with superior performance compared to the traditional method of using only cross-correlation. This method can exploit statistical knowledge of the timing noise such as loop bandwidth, giving further improvement in performance. View full abstract»

• ### An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement

Publication Year: 2008, Page(s):853 - 857
Cited by:  Papers (32)
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An active-frequency compensation circuit for low- dropout regulators (LDOs) is presented. Compared with the conventional compensation scheme, the proposed circuit can greatly boost the effective current multiplication factor by at least one order of magnitude without increasing any power consumption. Hence, the proposed circuit can generate an internal lower frequency zero and push parasitic poles... View full abstract»

• ### A Time-Interleaved $DeltaSigma$-DAC Architecture Clocked at the Nyquist Rate

Publication Year: 2008, Page(s):858 - 862
Cited by:  Papers (5)  |  Patents (1)
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This paper describes a delta-sigma (DeltaSigma) digital-to-analog converter (DAC) architecture that combines a polyphase decomposition of the interpolation filter and a time-interleaved error-feedback DeltaSigma modulator. Noise-shaped oversampling is achieved while clocking the digital circuitry at the Nyquist rate. The design of a third-order 4-bit modulator with eight times oversampling using t... View full abstract»

• ### On the Design of the Triple-Resonance Interstage Network

Publication Year: 2008, Page(s):863 - 866
Cited by:  Papers (3)
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The triple resonance network has emerged as a promising candidate for interstage bandwidth enhancement in cascaded CMOS amplifiers. This paper presents several design procedures for such networks, subject to the condition of moderate (1 dB) or no peaking in the passband, for the case where the devices can be chosen or designed, as well as the case in which the devices are given. View full abstract»

• ### Multidimensional Adaptive Power Management for Low-Power Operation of Wireless Devices

Publication Year: 2008, Page(s):867 - 871
Cited by:  Papers (14)
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Currently, wireless circuits are designed to meet minimum quality-of-service requirements under worst case wireless link conditions (interference, noise, multipath effects), leading to high power consumption when the channel is not worst case. In this work, we develop a multidimensional adaptive power management approach that optimally trades-off power versus performance across temporally changing... View full abstract»

• ### Interference Cancellation in Broadband Wireless Systems Utilizing Phase-Aligned Injection-Locked Oscillators

Publication Year: 2008, Page(s):872 - 876
Cited by:  Papers (6)
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We demonstrate an interferer suppression method based on feed-forward cancellation that uses an injection-locked oscillator (ILO) to extract interferers from the incident spectrum in an auxiliary receiver. The technique is expected to be useful in environments where a strong narrowband interferer appears along with a wideband desired signal, such as ultra-wideband (UWB) and emerging cognitive-radi... View full abstract»

• ### Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching

Publication Year: 2008, Page(s):877 - 881
Cited by:  Papers (17)
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We propose a new digital background calibration method for capacitor mismatches in pipelined analog-to-digital converters (ADCs). It combines commutated feedback capacitor switching with a background digital correlation loop to extract capacitor mismatch information, which is subsequently used to correct errors caused by the mismatch. This is an all-digital technique requiring minimal extra digita... View full abstract»

• ### Limit Cycles in a MEMS Oscillator

Publication Year: 2008, Page(s):882 - 886
Cited by:  Papers (16)
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In this paper, we apply methods of nonlinear dynamics to study the behavior of a microelectromechanical oscillator. We show how the analysis predicts the appearance of a devil's staircase-like relationship between frequencies, but also show how the output frequency of the oscillator, and hence the devil's staircase, may not be uniquely determined. Both of these features - the sequence of steps cor... View full abstract»

• ### Finding the Tuning Curve of a CMOS—LC VCO

Publication Year: 2008, Page(s):887 - 891
Cited by:  Papers (22)
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A nonlinear perturbation model of a complementary LC-tuned voltage-controlled oscillator is derived, which consists of two mutually-coupled second-order differential equations. The first-order approximate periodic solution of the describing equations is found, obtaining closed-form expressions for both the amplitude and the harmonics of oscillation, as well as for the correction of the oscillation... View full abstract»

• ### Switching Time in Relaxation Oscillations of Emitter-Coupled Multivibrators

Publication Year: 2008, Page(s):892 - 896
Cited by:  Papers (4)
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This paper gives an estimation of the switching time between on and off transistor states for the emitter-coupled multivibrator. The calculation uses the root locus of the characteristic equation for the oscillator small-signal equivalent circuit, while changing the device current as a parameter. The switching time is found using a fitting location of the root in the right half of the s-pla... View full abstract»

• ### VLSI Design of Diminished-One Modulo $2^{n}+1$ Adder Using Circular Carry Selection

Publication Year: 2008, Page(s):897 - 901
Cited by:  Papers (12)
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The diminished-one modulo 2n+1 addition is an important arithmetic operation for a high-performance residue number system. In this paper, we propose a new circular-carry-selection (CCS) technique for modulo 2n+1 addition in the diminished-one number domain. The architecture design of CCS modular adder is simple and regular for various bit-width inputs. For actual VLSI impleme... View full abstract»

• ### New Approach to Scalable Parallel and Pipelined Realization of Repetitive Multiple Accumulations

Publication Year: 2008, Page(s):902 - 906
Cited by:  Papers (2)
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In this brief, a new approach is presented for parallel and pipelined implementation of repetitive multiple accumulations; and used that further to derive two modular structures for high-throughput realization. A set of N input operands (to be accumulated) are converted into a set of L operands of M=log2(N+1) -bit size by using L number of M-bit... View full abstract»

• ### Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation

Publication Year: 2008, Page(s):907 - 911
Cited by:  Papers (22)
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This paper describes a method to numerically calculate the design margin and to estimate the yield associated with the read access failure for sub-100-nm SRAM. Process variations at sub-100 nm not only affect SRAM cells but also periphery circuits, such as the sense amplifier (SA) and the tracking scheme. Simulation that incorporates both SRAM cells and surrounding circuits is either accurate but ... View full abstract»

• ### Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture

Publication Year: 2008, Page(s):912 - 916
Cited by:  Papers (11)
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This paper presents an efficient real-time variable block size motion estimation architecture. The proposed architecture provides motion vectors for each 16 times 16 block and its 40 sub-blocks. The proposed architecture is a single-instruction multiple-data architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using Xilinx Virtex-4 XC4VSX35-10 field-program... View full abstract»

• ### High-Performance Low-Power Selective Precharge Schemes for Address Decoders

Publication Year: 2008, Page(s):917 - 921
Cited by:  Papers (4)
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Two novel address decoder schemes using selective precharging are presented and analyzed in this paper. These schemes, the AND-NOR and sense amplifier (sense-amp) decoders, are compared to the NOR decoder using 90-nm CMOS technology. The sense-amp decoder dissipates between 29.5% and 50.1% and the AND-NOR decoder dissipates between 73.7% and 104.4% of the energy dissipated by the NOR decoder. The ... View full abstract»

• ### A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

Publication Year: 2008, Page(s):922 - 926
Cited by:  Papers (3)  |  Patents (1)
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This work addresses power reduction and performance improvement for wireless orthogonal frequency-division multiplexing (OFDM) systems using a dynamic sample-timing controller (DSTC) and phase-tunable clock generator (PTCG). The receiver, applying the proposed DSTC algorithm, searches for the optimal sampling phase at the symbol rate, instead of the Nyquist rate (or higher), to reduce the extra po... View full abstract»

• ### Using Transmission Line Outage Data to Estimate Cascading Failure Propagation in an Electric Power System

Publication Year: 2008, Page(s):927 - 931
Cited by:  Papers (41)
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We study cascading transmission line outages recorded over nine years in an electric power system with approximately 200 lines. The average amount of propagation of the line outages is estimated from the data. The distribution of the total number of line outages is predicted from the propagation and the initial outages using a Galton-Watson branching process model of cascading failure. View full abstract»

• ### Global Synchronization and State Tuning in Asymmetric Complex Dynamical Networks

Publication Year: 2008, Page(s):932 - 936
Cited by:  Papers (10)
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A strategy to control the complex dynamical networks for global synchronization as well as to tune their synchronous states is presented based on linear state feedback controllers. The synchronous state can be changed from one system to other similar system just by choosing a suitable tuning matrix. Especially, some of the criteria are expressed in normal inequalities instead of matrix inequalitie... View full abstract»

• ### Analytical Stability Condition of the Latency Insertion Method for Nonuniform GLC Circuits

Publication Year: 2008, Page(s):937 - 941
Cited by:  Papers (17)
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The latency insertion method (LIM) is a transient simulation technique for circuits and is based on a finite-difference formulation, like the well-known finite-difference time-domain (FDTD) method for solving Maxwells equations. The LIM, like the FDTD method, is only conditionally stable resulting in an upper bound for the time step of the transient simulation. This bound on the time step is a fun... View full abstract»

• ### Second-Order Balanced Truncation for Passive-Order Reduction of RLCK Circuits

Publication Year: 2008, Page(s):942 - 946
Cited by:  Papers (13)
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In this paper, we propose a novel model-order reduction (MOR) approach, second-order balanced truncation (BT) for passive-order reduction (SBPOR), which is the first second-order BT method proposed for passive reduction of RLCK circuits. By exploiting the special structure information in the circuit formulation, second-order Gramians are defined based on a symmetric first-order realization in desc... View full abstract»

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org