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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 9 • Date Sept. 2008

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Displaying Results 1 - 23 of 23
  • Table of contents

    Publication Year: 2008 , Page(s): C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2008 , Page(s): C2
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  • Sensitivity Analysis for Oscillators

    Publication Year: 2008 , Page(s): 1521 - 1534
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1482 KB) |  | HTML iconHTML  

    This paper presents an analysis for calculating sensitivities of an oscillator's periodic steady state and perturbation projection vector to design, process, or environmental parameters. A general continuous-time formulation and time-domain numerical methods are described. The applications of the oscillator sensitivity analysis in design optimization, macromodeling, as well as in analyzing the impact of process variations are demonstrated through examples. View full abstract»

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  • A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models

    Publication Year: 2008 , Page(s): 1535 - 1544
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (989 KB) |  | HTML iconHTML  

    This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing. View full abstract»

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  • Generating Scalable and Modular Macromodels for Microchannels Using the Galerkin-Based Technique

    Publication Year: 2008 , Page(s): 1545 - 1554
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1333 KB) |  | HTML iconHTML  

    In this paper, we present a methodology of generating nonlinear microfluidic macromodels for system-level simulations of 3-D microchannels using the Galerkin-based technique. Each generated macromodel consists of a low-order model and a few basis functions. For generating the basis functions, the ensembles of snapshots of fluidic field distributions are calculated by a finite-element-method or finite-volume-method solver, and then, the proper orthogonal decomposition is employed to extract the basis functions from the ensembles. For creating the low-order model, the Galerkin condition is used to formulate a set of simple ordinary differential equations. Compared with the full-meshed simulations, the generated macromodels not only provide accurate results (i.e., about 1% error) but also give computational speedups of at least three orders of magnitude. Also, the scaling and reusability of the generated macromodels are described and discussed. Furthermore, the macromodels of complicated channels can also be created by assembling the macromodels of other simple channels. The errors between the results by the assembled macromodels and the results by the full-meshed models are less than 2%. View full abstract»

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  • Input Vector Reordering for Leakage Power Reduction in FPGAs

    Publication Year: 2008 , Page(s): 1555 - 1564
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (559 KB) |  | HTML iconHTML  

    In this paper, a leakage power reduction technique for field-programmable gate arrays (FPGAs) is proposed based on the state dependency property of leakage power. A pin reordering algorithm is proposed, where the subthreshold and gate leakage power components are taken into consideration to find the lowest leakage state for the FPGA pass-transistor multiplexers in the logic and routing resources without incurring any physical or performance penalties. The newly developed methodology is applied to several FPGA benchmarks, and an average leakage savings of 50.3% is achieved in a 90-nm CMOS process. Moreover, a modified version of the methodology is implemented to improve the performance of the final design, and again, considerable leakage power savings are achieved. Furthermore, the methodology is extended to find the lowest leakage states for several future predictive Berkeley CMOS technologies. View full abstract»

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  • IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level

    Publication Year: 2008 , Page(s): 1565 - 1570
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (555 KB) |  | HTML iconHTML  

    This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. The headroom of each disjoint closed cone is evaluated based on its slack and slack sustainability. The notion of slack sustainability in conjunction with an embedding threshold enables closed cones in the critical path to be qualified as watermark hosts if their slacks can be better preserved upon remapping. The watermark is embedded by remapping only qualified disjoint closed cones randomly selected and templates constrained by the signature. This parametric formulation provides a means to capitalize on the headroom of a design to increase the signature length or strengthen the watermark resilience. With the master design, the watermarked design can be authenticated as in nonoblivious media watermarking. Experimental results show that the design can be efficiently marked by our method with low overhead. View full abstract»

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  • Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process

    Publication Year: 2008 , Page(s): 1571 - 1582
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (746 KB) |  | HTML iconHTML  

    This paper presents a multiparameter moment-matching-based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi process (TAP). It is referred to as a Parameterized Interconnect Macromodeling via a TAP (PIMTAP) algorithm. PIMTAP inherits the advantages of previous multiparameter moment-matching algorithms and avoids their shortfalls. It is numerically stable and adaptive. PIMTAP model yields the same form of the original state equations and preserves the passivity of parameterized RLC networks like the well-known method passive reduced-order interconnect macromodeling algorithm for nonparameterized RLC networks. View full abstract»

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  • Nonconvex Gate Delay Modeling and Delay Optimization

    Publication Year: 2008 , Page(s): 1583 - 1594
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1064 KB) |  | HTML iconHTML  

    Convex delay models like the Elmore model, the related Logical Effort model, posynomial, and generalized posynomial models have always been favored by researchers, as convexity has a priori guarantees of global optimum solutions. The accuracy of the model may be sacrificed in this quest to generate convex delay models. In this paper, we investigate the use of signomial delay modeling for area/delay optimization. We present a procedure to automatically generate signomial gate delay models by nonlinear least squares fitting. As opposed to posynomial models, signomial models achieve better fits to SPICE generated data. However, signomials are not convex in general. Nevertheless, we show via duality arguments that we obtain near optimum (within 1%) solutions. Our optimization considers beta-ratio constraints, minimum and maximum size constraints for n- and p-transistors, rise/fall delays, and edge rates. The gate sizes for the fastest delay solution for a 44000-cell design, using the IBM 130-nm process, can be achieved in about 16 min of CPU time on a PC, and the area-delay tradeoff curve for 21 points can be generated in about 2 h of CPU time. To the best of our knowledge, this is the first report of using a true signomial delay model and its application to optimum gate sizing. In addition, we give performance details for the automatic data fitting for an 11-function library of static CMOS gates. View full abstract»

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  • Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method

    Publication Year: 2008 , Page(s): 1595 - 1606
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB) |  | HTML iconHTML  

    A new green function-based method for extracting parasitics in inhomogeneous substrates is presented. This approach overcomes the limitation of prior green function-based methods and allows extraction of substrate parasitics in the presence of sinkers, trenches, and wells. A careful use of volume and boundary-element meshing, as well as discrete transforms, yields a technique that is computationally efficient. The accuracy of the method is comparable to that of 3-D semiconductor device simulators with significantly smaller computational costs. View full abstract»

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  • BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms

    Publication Year: 2008 , Page(s): 1607 - 1620
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3204 KB)  

    BonnPlace is the placement tool of the University of Bonn, Germany. It is continuously used in the industry for the placement of most complex chips. Global placement is based on quadratic placement and multisection. Legalization of macros and standard cells uses minimum cost flow and dynamic programming algorithms. We describe details of our implementation and present new experimental results. View full abstract»

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  • MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs

    Publication Year: 2008 , Page(s): 1621 - 1634
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1323 KB) |  | HTML iconHTML  

    In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rates. Based on binary trees, the MP-tree is very efficient, effective, and flexible for handling macro placements with various constraints. Given a global placement that already considers the areas and the interconnections among standard cells and macros, our MP-tree-based macro placer optimizes macro positions, minimizes the macro displacement from the initial macro positions, and maximizes the area of the chip center for standard-cell placement and routing. Experiments based on the Proceedings of the 2006 International Symposium on Physical Design placement contest benchmarks and Faraday benchmarks show that our macro placer combined with APlace 2.0, Capo 10.2, mPL6, or NTUplace3 for a standard-cell placement outperforms these state-of-the-art academic mixed-size placers alone by large margins in robustness and quality. In addition to wirelength, experiments on four real industrial designs with large macros and high utilization rates show that our method significantly reduces the average half-perimeter wirelength by 35 %, the average routed wirelength by 55 %, and the routing overflows by 13 times compared with Capo 10.2, implying that our macro placer leads to much higher routability. View full abstract»

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  • Fast Dual-Graph-Based Hotspot Filtering

    Publication Year: 2008 , Page(s): 1635 - 1642
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (787 KB) |  | HTML iconHTML  

    As advanced technologies in wafer manufacturing push patterning processes toward lower subwavelength printing, lithography for mass production potentially suffers from decreased patterning fidelity. This results in the generation of many hotspots, which are actual device patterns with relatively large critical-dimension and image errors with respect to on-wafer targets. Hotspots can be formed under a variety of conditions such as the original design being unfriendly to the resolution enhancement technique that is applied, unanticipated pattern combinations in rule-based optical proximity correction (OPC), or inaccuracies in model-based OPC. When these hotspots fall on locations that are critical to the electrical performance of a device, device performance and parametric yield can be significantly degraded. The golden verification signoff tool using a simulation-based approach has occupied the mainstream and has been able to accurately detect hotspots. However, this approach represents a runtime-quality tradeoff point that is high in quality but also high in runtime. There is also little point in trying to replace the golden signoff tool. We are motivated to develop a low-runtime ldquo prefilterrdquo that reduces the amount of layout area to be analyzed by the golden tool, without compromising the overall quality of hotspot finding. In this paper, we first describe a novel detection algorithm for hotspots induced by lithographic uncertainty. Our goal is to rapidly detect all lithographic hotspots without significant accuracy degradation. In other words, we propose a filtering method: as long as there are no ldquofalse negatives,rdquo i.e., we reliably obtain a superset of actual hotspots, then our method can dramatically reduce the layout area processed by golden hotspot analysis. Our hotspot detection algorithm includes layout graph construction, graph planarization, three-level bridging hotspot detection, and necking hotspot detection. We have tested- - our flow on several industry test cases. The experimental results show that our method is promising: for benchmark designs in 90-nm and 65-nm technologies, 100% of bridging and open hotspots are detected with few falsely detected hotspots. The average runtime of our method is more than 496 faster compared to the commercial tool. View full abstract»

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  • Congestion-Constrained Layer Assignment for Via Minimization in Global Routing

    Publication Year: 2008 , Page(s): 1643 - 1656
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1520 KB) |  | HTML iconHTML  

    In this paper, we study the problem of layer assignment for via minimization, which arises during multilayer global routing. In addressing this problem, we take the total overflow and the maximum overflow as the congestion constraints from a given one-layer global routing solution and aim to find a layer assignment result for each net such that the via cost is minimized while the given congestion constraints are satisfied. To solve the problem, we propose a polynomial-time algorithm which first generates a net order and then performs layer assignment one net at a time according to the order using dynamic programming. Our algorithm is guaranteed to generate a layer assignment solution satisfying the given congestion constraints. We used the six-layer benchmarks released from the ISPD'07 global routing contest to test our algorithm. The experimental results show that our algorithm was able to improve the contest results of the top three winners MaizeRouter, BoxRouter, and FGR on each benchmark. As compared to BoxRouter 2.0 and FGR 1.1, which are newer versions of BoxRouter and FGR, our algorithm respectively produced smaller via costs on all benchmarks and half the benchmarks. Our algorithm can also be adapted to refine a given multilayer global routing solution in a net-by-net manner, and the experimental results show that this refinement approach improved the via costs on all benchmarks for FGR 1.1. View full abstract»

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  • Diagnosis of Optical Lithography Faults With Product Test Sets

    Publication Year: 2008 , Page(s): 1657 - 1669
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1390 KB) |  | HTML iconHTML  

    Increasing within-die variation, combined with larger numbers of critical and near-critical paths and higher operating frequencies, has increased the sensitivity of chips to path delay faults. A component of within-die variation comes from optical lithography, including the optical proximity effect, lens aberrations, and flare. This paper presents a methodology to generate test sets to diagnose these sources of within-die variation. Specifically, a delay fault diagnosis algorithm is developed to link failing signatures to a set of physical mechanisms originating from lithography. The algorithm relies on layout-dependent timing analysis, path enumeration, test pattern generation, and correlation of pass/fail signatures to diagnose delay faults caused by lithography. The effectiveness of diagnosis is evaluated for ISCAS85 benchmark circuits. View full abstract»

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  • Automatic Verification of External Interrupt Behaviors for Microprocessor Design

    Publication Year: 2008 , Page(s): 1670 - 1683
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1211 KB) |  | HTML iconHTML  

    Interrupt behaviors, particularly the external ones, are difficult to verify in a microprocessor. Because the external interrupt arrival time and the microprocessor response time must be precise, verification requires sophisticated hardware and software design. This paper proposes a computer-aided design tool, called processor exception verification tool (PEVT), to verify the external interrupt behaviors of microprocessors, including individual, multiple, and nested interrupts. An architecture description language extension, called Exception Description Language (EXPDL), is developed for the designer to capture the external interrupt behaviors for the microprocessor under verification. PEVT is responsible for generating the verification cases, consisting of both the hardware and software modules, which are then used to trigger the expected behaviors. A monitor is also generated from the EXPDL description to verify these cases. PEVT has been applied to the verification of an academic implementation of the ARM7 microprocessor core and a public domain scalable processor architecture (SPARC) microprocessor core. The ARM7 has had a system-on-a-chip test chip and software porting including multimedia applications (MP3/JPEG/ ...) and a real time operating system muC-OSII. PEVT successfully identified several sophisticated remaining bugs with 527 lines of EXPDL description and took only 4 204 961 cycles of register transfer language simulation with execution time of 4.5 h in a SUN Blade2000 workstation. The experiment shows that PEVT could generate highly focused verification cases, less than 98 cycles per case on the average, which identify potential bugs with much less simulation cycles at the early verification stage, compared with traditional manual-based approaches. View full abstract»

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  • A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs

    Publication Year: 2008 , Page(s): 1684 - 1688
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB) |  | HTML iconHTML  

    A compact RF CMOS model incorporating an improved thermal noise model is developed. Short-channel effects (SCEs), substrate potential fluctuation effect, and parasitic-resistance-induced excess noises were implemented in analytical formulas to accurately simulate RF noises in sub-100-nm MOSFETs. The intrinsic noise extracted through a previously developed lossy substrate de-embedding method and calculated by the improved noise model can consistently predict gate length scaling effects. For 65- and 80-nm n-channel MOS with fT above 160 and 100 GHz, NFmin at 10 GHz can be suppressed to 0.5 and 0.7 dB, respectively. Drain current noise Sid reveals an apparently larger value for 65-nm devices than that for 80-nm devices due to SCE. On the other hand, the shorter channel helps reduce the gate current noise Sig attributed to smaller gate capacitances. Gate resistance Rg-induced excess noise dominates in Sig near one order higher than the intrinsic gate noise that is free from Rg for 65-nm devices. The compact RF CMOS modeling can facilitate high-frequency noise simulation accuracy in nanoscale RF CMOS circuits for low-noise design. View full abstract»

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  • Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs

    Publication Year: 2008 , Page(s): 1689 - 1692
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB) |  | HTML iconHTML  

    Linear finite-state machines (LFSMs) such as linear feedback shift registers (LFSRs), cellular automata (CA), and ring generators (RGs) are used as test pattern generators in built-in self-test schemes that employ 2-D scan design. These mechanisms are usually accompanied by phase shifters (PSs) in order to avoid the degradation of the fault coverage caused by correlations/dependences in the produced test bit sequences. Given this context, we investigate in this paper the potential of generalized (or Galois) LFSRs (GLFSRs) as onboard test pattern generators. We compare GLFSRs with and without PSs against LFSMs with PSs (LFSM/PSs) for various types of LFSMs (LFSRs, CA, RGs, and dense RGs) on two accounts: channel separation and overall hardware cost. Experimental results show that GLFSRs achieve larger channel separation with lower hardware cost than LFSM/PS and attain higher fault coverage. View full abstract»

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  • Testing Transition Delay Faults in Modified Booth Multipliers

    Publication Year: 2008 , Page(s): 1693 - 1697
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (350 KB) |  | HTML iconHTML  

    This paper proposes a novel type of modified Booth multiplier and generates constant test pairs for single transition delay faults (TDFs) in multipliers of various sizes. All TDFs of the multipliers at cell and gate levels are C-testable with 10 and 27 patterns, respectively. These patterns can be generated by using a linear feedback shift register or a finite state machine, requiring a modest increase of 5% area for our 32 X 32 multiplier, for example. In addition, a method is proposed to generate 51% to 99% fewer patterns for the realistic sequential cell fault model (RS-CFM), when compared with a recent work. RS-CFM faults, which are claimed to be comprehensive in modeling sequential fault effects inside the cells, require all possible single-input-change patterns prepared for each cell. The proposed method generates 104 + 10 X Ny test pairs for RS-CFM in the Nx X Ny modified Booth multiplier to achieve a similar fault coverage as the cited work. View full abstract»

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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2008 , Page(s): 1698
    Save to Project icon | Request Permissions | PDF file iconPDF (25 KB)  
    Freely Available from IEEE
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    Publication Year: 2008 , Page(s): 1699
    Save to Project icon | Request Permissions | PDF file iconPDF (270 KB)  
    Freely Available from IEEE
  • Have you visited lately? www.ieee.org [advertisement]

    Publication Year: 2008 , Page(s): 1700
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    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2008 , Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (27 KB)  
    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu