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Solid-State Circuits, IEEE Journal of

Issue 8 • Date Aug. 2008

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Displaying Results 1 - 21 of 21
  • Table of contents

    Page(s): C1
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    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits publication information

    Page(s): C2
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    Freely Available from IEEE
  • Table of contents

    Page(s): 1713
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  • Introduction to the Special Issue on the IEEE 2007 Custom Integrated Circuits Conference

    Page(s): 1714 - 1716
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    Freely Available from IEEE
  • A Wideband W-Band Receiver Front-End in 65-nm CMOS

    Page(s): 1717 - 1730
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2544 KB) |  | HTML iconHTML  

    A 75-to-91 GHz receiver front-end, consisting of a three-stage cascode low-noise amplifier (LNA), a double-balanced Gilbert-cell mixer and a differential DC-to-9 GHz IF buffer, is reported in 65-nm general purpose (GP) CMOS technology. The noise and input-impedance matched LNA employs a cascode input stage with shunt-series, transformer feedback. A theoretical and experimental comparison with a conventional inductor-feedback LNA indicates 0.5-1 dB higher gain, 0.3-0.6 dB lower noise figure and better input return loss for the transformer feedback LNA. The receiver has a differential down-conversion gain of 13 dB, an input P1dB of -16.2 dBm, and a double-sideband noise figure of 8.5 to 10 dB at an IF of 1 GHz. Because of the transformer feedback, the input return loss is better than -20 dB from 80 to 92 GHz and remains below -10 dB from 70 GHz beyond 95 GHz. The circuit occupies an area of 460 mum times 500 mum and consumes 89 mW (47 mW in the LNA and mixer) from a 1.5 V supply. An LO-to-RF isolation of 60 dB was measured for LO signals in the 80-to-85 GHz range. Measurements of the mixer breakout, which includes transformers at the RF and LO ports, show a record NFDSB of 8 to 10 dB over the 74-to-91 GHz band. The 50-Omega noise figure of the LNA is 6.4 to 8.4 dB in the 75-to-88.5 GHz range. The LNA can also be employed as a transmitter output stage with a saturated output power of +4 dBm. View full abstract»

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  • A Versatile, Low Power, High Performance BiCMOS MIMO/Diversity Direct Conversion Transceiver IC for WiBro/WiMAX (802.16e)

    Page(s): 1731 - 1740
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2466 KB) |  | HTML iconHTML  

    This paper describes a dual signal path (MIMO) low power, high performance direct conversion WiBro/WiMAX 802.16 e radio transceiver optimized for mobile applications and for coexistence with co-located cellular and WLAN/Bluetooth systems. The direct-conversion transceiver is designed to be very flexible in respect of biasing and programmability, both to allow power consumption to be traded adaptively versus performance, and flexibility for any changes in the new transmission standard. Signal loopback and transmit power detection techniques are used in conjunction with the baseband modem processor to calibrate transmitter LO leakage and the transceiver and receiver IQ imbalances. The receiver achieves a noise figure (NF) of less than 2.5 dB over an operational frequency range of 2.3-2.7 GHz, and the gain is tunable from 0 dB to 97 dB in 1 dB steps. The maximum linear transmit power is 2.5 dBm and the transmit gain can be digitally controlled over a 75 dB range. The transceiver is fabricated in a 0.25 mum SiGe BiCMOS process and consumes 65/103 mA from a 2.8 V supply in OFDMA Rx/Tx modes, respectively. View full abstract»

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  • A Single-Chip UHF RFID Reader in 0.18 \mu{\hbox {m}} CMOS Process

    Page(s): 1741 - 1754
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3149 KB) |  | HTML iconHTML  

    A single-chip UHF RFID reader that integrates all building blocks-including an RF transceiver, IQ data converters, and a digital baseband-is implemented in a 0.18 mum CMOS process. A high-linearity RX front-end and a low-phase-noise synthesizer are proposed to handle the large self-interferer, which is a key challenge in the reader RX design. Highly reconfigurable mixed-signal baseband architecture for channel-selection filtering is proposed to achieve power optimization for multi-protocol operation with different system dynamic ranges and data rates. The reader dissipates a maximum power of 276.4 mW when transmitting maximum output power of 10.4 dBm and receiving the tag's response of -70 dBm in the presence of -5 dBm self-interferer while occupying 18.3 mm2. View full abstract»

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  • A 30.5 dBm 48% PAE CMOS Class-E PA With Integrated Balun for RF Applications

    Page(s): 1755 - 1762
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2749 KB) |  | HTML iconHTML  

    Integration of the power amplifier together with signal processing in a transmitter is still missing in demanding RF commercial products. Issues preventing PA integration include LO pulling phenomena, thermal dissipation, and power efficiency. In this work we investigate high efficiency watt range Class-E PAs and integrated baluns. In particular, insights in the design of a fully differential cascode topology for high efficiency and reliable operation are provided and a narrowband lumped element balun, employing minimum number of integrated inductors for minimum power loss, is introduced. Two versions have been manufactured using a 0.13 mum CMOS technology. The first comprises the driver, and a differential PA connected to an external low-loss commercial balun. Experiments prove 31 dBm delivered output power, with 58% PAE and 67% drain efficiency, at 1.7 GHz. The second version adopts the same driver and PA and also integrates the balun. Experiments prove 30.5 dBm delivered output power, with 48% PAE and 55% drain efficiency, at 1.6 GHz. View full abstract»

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  • A 2.5 Gb/s Run-Length-Tolerant Burst-Mode CDR Based on a 1/8th-Rate Dual Pulse Ring Oscillator

    Page(s): 1763 - 1771
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1428 KB) |  | HTML iconHTML  

    A 2.5 Gb/s burst-mode clock and data recovery (CDR) circuit is presented that uses a 1/8th-rate ring oscillator with two pulses running simultaneously that are phase independent. One ldquotunerdquo pulse sets the delay of the ring by phase locking it to a reference. The other ldquoclockrdquo pulse tracks the phase of the incoming data by a process of pulse removal and reinsertion. Because both pulses share the same ring, there is no frequency mismatch between the incoming data stream and the recovered clock in frequency synchronous systems, allowing for large data run lengths. A 1:8 data-demux clock is naturally generated by tapping the clock pulse along the ring. Phase acquisition is instantaneous from a single data edge. Run length tolerance is larger than 72 bits. The 0.6 mm2 0.13 mum CMOS chip includes a CML-to-CMOS input buffer, PLL with on-chip loop filter, PRBS checker, 1:8 data demux, and eight output buffers. It has 2.7 UIpp measured jitter tolerance at 100 kHz and consumes 42 mW from a single 1.2 V supply. View full abstract»

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  • A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR

    Page(s): 1772 - 1782
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    In this paper, analysis and design of a four-bit fourth- order delta-sigma modulator with a widely programmable center frequency are presented. Novel methods for quantizing and implementing the digitally programmable modulator coefficients enable performance comparable to state-of-the-art discrete-time fixed- frequency modulators at any center frequency from DC to 0.31 fs in steps of 0.0052 fs. The 0.18 mum 1.8 V CMOS prototype implemented in a silicon area of 4.5 mm 2 consumes 115 mW at a sampling frequency of 40 MHz. The SNDR and SNR over a 310 kHz bandwidth range from 71 dB to 82 dB and from 76 dB to 86 dB, respectively. View full abstract»

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  • A 63 mA 112/94 dB DR IF Bandpass \Delta \Sigma Modulator With Direct Feed-Forward Compensation and Double Sampling

    Page(s): 1783 - 1794
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    We developed a 10.7 MHz intermediate frequency bandpass discrete-time 4th-order 4-bit DeltaSigma modulator for AM/FM car radio tuners. Using direct feed-forward compensation and double sampling, we have achieved a dynamic range (DR) of 112 dB in the 3 kHz AM bandwidth (BW) and a DR of 94 dB in the 200 kHz FM BW. The modulator occupies 3 mm2 , in 0.15 mum CMOS technology, and draws 63 mA of current. View full abstract»

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  • Integrated Regulation for Energy-Efficient Digital Circuits

    Page(s): 1795 - 1807
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (479 KB) |  | HTML iconHTML  

    Despite their use in analog or mixed-signal applications, the high power overheads of traditional linear regulators (both series and shunt) have precluded their successful adoption in regulating the supply of energy-efficient digital circuits. In this paper, we show that linear regulation can in fact reduce the effective supply impedance of digital circuits without increasing their total power dissipation. Achieving this goal requires minimizing the static power dissipation of the regulator, leading to a push-pull topology (similar to the regulators demonstrated by Wu and Sanders, 2001, Poon et al, 1999, and Intersil, 1998) with comparator-based feedback and a switched source-follower output stage. Measured results from a regulator implemented in a 65 nm SOI test-chip verify that by using these techniques, regulation reduces the effective supply noise by ~30% while also enabling a slight decrease (1.4%) in total power dissipation. View full abstract»

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  • An EEPROM Programming Controller for Passive UHF RFID Transponders With Gated Clock Regulation Loop and Current Surge Control

    Page(s): 1808 - 1815
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1158 KB) |  | HTML iconHTML  

    This paper presents an EEPROM programming controller imbedded in a passive UHF RFID transponder. A 14 V programming voltage is generated and regulated for a 224-bit EEPROM memory array from a rectified voltage supply of 2-3 V. A gated clock regulation loop is proposed to keep the programming voltage constant over a wide range of received RF input power, in order to improve the write-erase endurance of the memory. A current surge control scheme is proposed to allow the EEPROM programming voltage ramping in steps, therefore, preventing the collapse of the rectified supply in the remotely powered transponder. Also presented is a nano-power switched bandgap reference to reduce die area through the reduction of MOmega resistors needed for nano-power operation. Measurement results show that a 0.35 mum CMOS transponder IC provides a stable EEPROM programming voltage which varies less than 8% over a large 30 dB input power range while consuming 7 muW. The EEPROM programming controller occupies 0.092 mm2 die area. View full abstract»

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  • Simple Statistical Analysis Techniques to Determine Optimum Sense Amp Set Times

    Page(s): 1816 - 1825
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (746 KB) |  | HTML iconHTML  

    Statistical analysis techniques are described, involving a relatively small number of actual circuit simulations, to accurately determine the optimum sense amp set time for SRAM designs. Techniques to generate and evaluate the statistical distributions for bit line leakage, signal development, sense amp asymmetry and timing fluctuations in control circuits are discussed with important implications to sense amp design. The procedure is outlined in detail using representative circuits and simulations from a 65 nm CMOS bulk technology. View full abstract»

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  • A 180 Kbit Embeddable MRAM Memory Module

    Page(s): 1826 - 1834
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1894 KB) |  | HTML iconHTML  

    A 180 Kbit magnetoresistive random access memory (MRAM) organized as 22 bits by 8 Kwords has been developed for embedding in a 0.28 micron CMOS process. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell with a toggle MTJ. For reads, the memory is architected with word lines connecting a row of bits to bit lines with a pass transistor and two stages of columns selection transistors connecting bit lines to dual sense amplifiers. For writes, a read is first performed to determine the state of bits to be written followed by a toggle decision to enable bit line toggle drivers. Overlapping bit and word line currents toggle the selected bits. The new dual sense amplifier architecture separates the amplifier reference bits from the bias bits thereby improving sensitivity and reducing offset. The write driver uses a switched capacitor and charge sharing to improve ground bounce immunity and reduce area. Embedded test registers control internal memory timing, reference voltages, reference currents and access features enabling detailed characterization of the memory and optimization of the design. An example describing optimization of the write parameters is presented. View full abstract»

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  • Power Reduction Techniques for LDPC Decoders

    Page(s): 1835 - 1845
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1099 KB) |  | HTML iconHTML  

    This paper investigates VLSI architectures for low-density parity-check (LDPC) decoders amenable to low-voltage and low-power operation. First, a highly-parallel decoder architecture with low routing overhead is described. Second, we propose an efficient method to detect early convergence of the iterative decoder and terminate the computations, thereby reducing dynamic power. We report on a bit-serial fully-parallel LDPC decoder fabricated in a 0.13-mum CMOS process and show how the above techniques affect the power consumption. With early termination, the prototype is capable of decoding with 10.4 pJ/bit/iteration, while performing within 3 dB of the Shannon limit at a BER of 10-5 and with 3.3 Gb/s total throughput. If operated from a 0.6 V supply, the energy consumption can be further reduced to 2.7 pJ/bit/iteration while maintaining a total throughput of 648 Mb/s, due to the highly-parallel architecture. To demonstrate the applicability of the proposed architecture for longer codes, we also report on a bit-serial fully-parallel decoder for the (2048, 1723) LDPC code in 10 GBase-T standard synthesized with a 90-nm CMOS library. View full abstract»

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  • A High-Throughput Maximum a Posteriori Probability Detector

    Page(s): 1846 - 1858
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    This paper presents a maximum a posteriori probability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and, with Turbo processing, can approach performance close to the channel capacity limit. The implementation benefits from optimizations performed at both algorithm and circuit level. The proposed detector utilizes a deep-pipelined architecture implemented in skew-tolerant domino and experimentally measured results verify the detector can achieve throughputs greater than 750 Mb/s while consuming 2.4 W. The 16-state EEPR4 channel detector is implemented in a 0.13 mum CMOS technology and has a core area of 7.1 mm2. View full abstract»

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  • Active CMOS Sensor Array for Electrochemical Biomolecular Detection

    Page(s): 1859 - 1871
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1770 KB) |  | HTML iconHTML  

    Electrochemical sensing of biomolecules eliminates the need for the bulky and expensive optical instrumentation required in traditional fluorescence-based sensing assays. Integration of the sensor interface electrodes and active electrochemical detection circuitry on a CMOS substrate miniaturizes the sensing platform, enhancing its portability for use in point-of-care applications, while enabling the high-throughput, highly parallel analysis characteristic of traditional microarrays. This paper describes the design of a four-by-four active sensor array for multiplexed electrochemical biomolecular detection in a standard 0.25-mum CMOS process. Integrated potentiostats, comprised of control amplifiers and dual-slope analog-to-digital converters, stimulate the electrochemical cell and detect the current flowing through the on-chip gold electrodes at each sensor site that results from biomolecular reactions occurring on the chip surface. Post-processing steps needed to fabricate a biologically-compatible surface-electrode array in CMOS that can withstand operation in a harsh electrochemical environment are also described. Experimental results demonstrating the proper operation of the active CMOS array for biomolecular detection include cyclic voltammetry of a reversible redox species, DNA probe density characterization, as well as quantitative and specific DNA hybridization detection. View full abstract»

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  • ISSCC 2009 call for papers

    Page(s): 1872
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    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits information for authors

    Page(s): C3
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    Freely Available from IEEE
  • Blank page [back cover]

    Page(s): C4
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    Freely Available from IEEE

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan