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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 8 • Date Aug. 2008

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2008, Page(s): C1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2008, Page(s): C2
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  • Satisfiability Models for Maximum Transition Power

    Publication Year: 2008, Page(s):941 - 951
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (546 KB) | HTML iconHTML

    A satisfiability-based technique for symbolic modeling of event propagation in a circuit is presented in this paper which captures the events in the internal nodes of the circuit with a high level of detail. The model is used to accurately measure the peak single cycle transition power consumption in combinational and sequential circuits, which is closely affected by the switching activity in the ... View full abstract»

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  • Energy-Aware Flash Memory Management in Virtual Memory System

    Publication Year: 2008, Page(s):952 - 964
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1396 KB) | HTML iconHTML

    The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage. Recently, flash memory becomes a popular storage alternative for many portable devices with the continuing improvements on its capacity, reliability and much lower power consumption than mechanical hard drives. The characteristics of flash memory are quite different from a magnetic disk... View full abstract»

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  • Hybrid-Type CAM Design for Both Power and Performance Efficiency

    Publication Year: 2008, Page(s):965 - 974
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB) | HTML iconHTML

    Content-addressable memory (CAM) is a hardware table that can compare the search data with all the stored data in parallel. Due to the parallel comparison feature where a large amount of transistors are active on each lookup, however, the power consumption of CAM is usually considerable. This paper presents a hybrid-type CAM design which aims to combine the performance advantage of the NOR-type CA... View full abstract»

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  • A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing

    Publication Year: 2008, Page(s):975 - 984
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB) | HTML iconHTML

    Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact on the yield of the integrated circuits and need to be considered early in the design flow. Traditional corner based deterministic methods are no longer effective and circuit optimization methods require reinvention with a statistical ... View full abstract»

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  • Energy Budget Approximations for Battery-Powered Systems With a Fixed Schedule of Active Intervals

    Publication Year: 2008, Page(s):985 - 998
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (783 KB) | HTML iconHTML

    The amount of available energy is a critical limitation of battery-powered electronic systems. The classic design goal is to minimize system energy consumption subject to performance constraints. An alternative objective would be to maximize performance under energy constraints, which requires a method for computing the energy budget corresponding to a certain battery lifetime. This paper p... View full abstract»

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  • Cost-Efficient SHA Hardware Accelerators

    Publication Year: 2008, Page(s):999 - 1008
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (749 KB) | HTML iconHTML

    This paper presents a new set of techniques for hardware implementations of secure hash algorithm (SHA) hash functions. These techniques consist mostly in operation rescheduling and hardware reutilization, therefore, significantly decreasing the critical path and required area. Throughputs from 1.3 Gbit/s to 1.8 Gbit/s were obtained for the SHA implementations on a Xilinx VIRTEX II Pro. Compared t... View full abstract»

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  • Improving Error Tolerance for Multithreaded Register Files

    Publication Year: 2008, Page(s):1009 - 1020
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (735 KB) | HTML iconHTML

    Chip multithreaded computing is exposed to the dual challenges of increasing system complexity and error sensitivity. It is critical to develop effective solutions that achieve better error tolerance without inducing performance degradation. In this paper, we propose a new error-tolerant memory design based on a unique computing phenomenon referred to as the dynamic multithreading redundancy (DMR)... View full abstract»

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  • TDM Virtual-Circuit Configuration for Network-on-Chip

    Publication Year: 2008, Page(s):1021 - 1034
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (899 KB) | HTML iconHTML

    In network-on-chip (NoC), time-division-multiplexing (TDM) virtual circuits (VCs) have been proposed to satisfy the quality-of-service requirements of applications. TDM VC is a connection-oriented communication service by which two or more connections take turns to share buffers and link bandwidth using dedicated time slots. In the paper, we first give a formulation of the multinode VC configurati... View full abstract»

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  • Automatic Test Generation for Combinational Threshold Logic Networks

    Publication Year: 2008, Page(s):1035 - 1045
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (997 KB) | HTML iconHTML

    We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs), single electron transistor (SET), and quantum cellular automata (QCA), implement threshold logic. Consequently, there is a need to develop an ATPG methodology for this t... View full abstract»

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  • MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip

    Publication Year: 2008, Page(s):1046 - 1057
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1701 KB) | HTML iconHTML

    The rapid migration to nanometer design processes has brought an unprecedented level of integration by allowing system designers to pack a wide variety of functionalities on-chip, namely, systems-on-a-chip (SoCs). In the meantime, electronic testing becomes an enabling technology for this SoC paradigm, since the integration of various core tests is a big challenge, and has revealed a widening gap ... View full abstract»

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  • Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

    Publication Year: 2008, Page(s):1058 - 1071
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2052 KB) | HTML iconHTML

    This investigation proposes a novel radix-42 algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-42 single delay feedback path (R42SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algo... View full abstract»

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  • Configurable VLSI Architecture for Deblocking Filter in H.264/AVC

    Publication Year: 2008, Page(s):1072 - 1082
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2363 KB) | HTML iconHTML

    In this paper, we study and analyze the computational complexity of the deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations, and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performanc... View full abstract»

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  • Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA

    Publication Year: 2008, Page(s):1083 - 1090
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB) | HTML iconHTML

    Increasing device densities have prompted FPGA manufacturers, such as Xilinx and Altera, to incorporate larger embedded components, including multipliers, DSP blocks and even embedded processors. One of the recent architectural enhancements in the Xilinx Virtex family architecture is the introduction of the PowerPC405 hard-core embedded processor. In this paper we present a software defined radio ... View full abstract»

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  • Transition Skew Coding for Global On-Chip Interconnect

    Publication Year: 2008, Page(s):1091 - 1096
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (513 KB) | HTML iconHTML

    This paper presents new simulation results of the previously proposed transition skew coding (TSC) for global on-chip interconnects. Considering 2-GHz global clock frequency at the 90-nm node, we show that TSC can be applied to broad range of wire length on both semiglobal and global metal layers, while maintaining its energy efficiency and its advantages in terms of crosstalk reduction and signal... View full abstract»

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  • Effective Uses of FPGAs for Brute-Force Attack on RC4 Ciphers

    Publication Year: 2008, Page(s):1096 - 1100
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (125 KB) | HTML iconHTML

    This paper presents an effective field-programmable gate array (FPGA)-based hardware implementation of a parallel key searching system for the brute-force attack on RC4 encryption. The design employs several novel key scheduling techniques to minimize the total number of cycles for each key search and uses on-chip memories of the FPGA to maximize the number of key searching units per chip. Based o... View full abstract»

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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2008, Page(s): C3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2008, Page(s): C4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu