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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 7 • Date July 2008

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Displaying Results 1 - 25 of 27
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Page(s): C2
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  • A Low-Supply-Voltage CMOS Sub-Bandgap Reference

    Page(s): 609 - 613
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (195 KB) |  | HTML iconHTML  

    A low-power (21 muW ) bandgap reference source that is operable from a nominal supply voltage of 1.4 V is described. The circuit provides an output voltage equal to the bandgap voltage having a low output resistance and allows resistive loading. It does not use resistors or operational amplifiers. Thus, the design is suitable for fabrication in any digital CMOS technology. The circuit uses a current conveyor and current mirrors to convert the proportional to absolute temperature voltage into a current using a MOSFET. The current is converted back to a voltage by using the functional inverse of the FET v-i characteristics. This makes the voltage gain linear and temperature independent. The absence of back-gate bias is the reason for achieving the low supply voltage of operation. Simulation results using the transistor models for the 0.18-mum TSMC process show that the voltage-variation over the temperature range 0 to 100degC is <1 mV. View full abstract»

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  • A Current-Mode Comparator for Digital Calibration of Amorphous Silicon AMOLED Displays

    Page(s): 614 - 618
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    We present a digital calibration driving scheme for stabilizing the uniformity of large area amorphous silicon active-matrix organic light emitting diode displays. A current-mode analog-to-digital converter (ADC) is used to extract the differential aging of the individual pixels. For the ADC, a configurable current comparator is designed that employs the output buffer of the source driver to reduce the die area. The comparator and pixel circuit were fabricated in 0.8-mum high-voltage CMOS and amorphous silicon technologies, respectively. Analysis and measurement results show a calibration refresh time of 2 s for a high-definition display (1920 times RGB times 1080). Moreover, the pixel current is highly stable despite a 5-V shift in the threshold voltage of the thin-film transistor driver. View full abstract»

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  • On the Spectral Tones in a Digital-Analog Converter Due to Mismatch and Flicker Noise

    Page(s): 619 - 623
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (574 KB) |  | HTML iconHTML  

    Spurious-free dynamic range (SFDR) is one of the most important design metrics for a high-performance digital-analog converter (DAC). SFDR is limited by both dynamic (switching) and static (mismatch) nonlinearities. A good design needs to ensure that the spurious spectral tones caused by the static mismatches do not limit the performance. Aggressively scaling device sizes have also aggravated the problem of flicker noise, which gets modulated by the signal and presents itself as spectral tones. Typically, time domain statistical simulations are needed to guarantee system performance in presence of these nonidealities. In this work, we present a theoretical approach to compute these spectral tones. View full abstract»

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  • Analysis and Implementation of a 0.9-V Voltage-Controlled Oscillator With Low Phase Noise and Low Power Dissipation

    Page(s): 624 - 627
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    A voltage-controlled oscillator (VCO) with low phase noise and low power dissipation for IEEE 802.11b is proposed. A negative resistance multiple-gated circuit with a bypass capacitor is adopted to improve phase noise. The chip is implemented in 0.18-mum CMOS process under a supply voltage of 0.9 V and power consumption of 2.7 mW. Its measured results show that the VCO has a phase noise of -122.3 dBc/Hz at 1-MHz offset frequency from the carrier frequency, and the tuning frequency from 2.17 to 2.73 GHz can be obtained under the tuning voltage of -0.9 to 0.9 V. The theoretical analysis and design consideration are also conducted in detail to show the benefits of the proposed VCO. View full abstract»

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  • Wien-Type Oscillators: Evaluation and Optimization of Harmonic Distortion

    Page(s): 628 - 632
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    Theoretical study and design strategy for Wien oscillator circuits are presented. The analysis takes into account nonlinearities and allows to define an optimum design procedure minimizing distortion. The accuracy and viability of both the proposed analysis and design approach are confirmed experimentally. View full abstract»

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  • A 5-GHz Subharmonic Injection-Locked Oscillator and Self-Oscillating Mixer

    Page(s): 633 - 637
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    This paper presents a multifunctional circuit realizing the functions of oscillation, mixing, amplification, and frequency multiplication at 5 GHz. A theoretical and experimental description of the circuit is given. The proposed circuit, which combines both the injection-locking and mixing processes, uses only one port where both the RF/intermediate frequency signal and the injection signal (IS) are applied. The IS, which is used to stabilize the oscillation, is at a subharmonic of the oscillation frequency (omegaosc/4) having a power level as low as -50 dBm. Calculations of the phase noise and measurements of the mixing properties are reported which indicate a noise improvement, and a high up-conversion gain. The implementation of the circuit exhibits an up-conversion gain of 14 dB, a phase noise of -110 dBc/Hz at 100-kHz offset, a dB of -15 dBm, a third-order intercept point of -2 dBm, and a power consumption of 35 mW. Calculated and measured results are in good agreement for all cases, emphasizing the relevance of the proposed circuit. View full abstract»

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  • Experimental Analysis of Substrate Noise Effect on PLL Performance

    Page(s): 638 - 642
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (990 KB) |  | HTML iconHTML  

    This paper describes experimental approaches to analyze the effect of the substrate noise on phase-locked loop (PLL) performance. Spectral analysis considering noise transfer functions of the PLL is used to identify the substrate-noise sensitive components of the PLL. Analyzing the sidebands seen in a spectrum analyzer confirms the importance of knowing the PLL loop dynamics and noise transfer functions. It also leads to the conclusion that the PLL blocks other than the VCO can be more sensitive to substrate noise coupling, depending on the substrate noise frequency. Furthermore, the result shows that intermodulation near the reference clock frequency could be a dominant source of generating sidebands in fractional-N PLLs. View full abstract»

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  • Wireless Dosimeter: System-on-Chip Versus System-in-Package for Biomedical and Space Applications

    Page(s): 643 - 647
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1312 KB) |  | HTML iconHTML  

    A new floating-gate (FG) MOSFET based wireless dosimeter system-in-package (SiP) is presented. This miniature and completely integrated wireless dosimeter SiP comprises a CMOS FG radiation sensor and transmitter (TX) in a low-temperature co-fired ceramic (LTCC) package. The design is very well suited to wireless transmission of radiation sensor data in radiotherapy and to Extra Vehicular Activity Radiation Monitoring (EVARM) in space. Two different solutions, namely system-on-chip (SoC) and SiP, are demonstrated. In the SoC, which is size and power efficient, the TX includes an on-chip loop antenna which also acts as the inductor for the VCO resonant tank circuit. The SiP solution has an LTCC antenna with optimized impedance to conjugate match the TX chip. The radiation sensor demonstrates a measured sensitivity of 5 mV/rad. The SoC module size is only 2 mm2, consumes 5.3 mW of power and delivers -0.9 dBm of radiated power, sufficient to communicate with a low noise receiver connected to an off-chip patch antenna placed 1.38 m away. The SiP design provides a larger communication range of 75 m at the cost of additional power consumption and size. View full abstract»

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  • Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch

    Page(s): 648 - 652
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (690 KB) |  | HTML iconHTML  

    Time interleaving is one of the most efficient techniques employed in the design of high-speed sampled-data systems. However, the mismatches appearing among different channels will create distortion tones that will degrade the system performance. This paper presents a detailed analysis of the effect of sampling bandwidth mismatches in the statistical behavior of time-interleaved sampling systems. Closed-form and handy signal-to-noise distortion ratio formulas will also be derived which allow quick evaluation of the system performance, and the MATLAB simulations are provided in order to verify the effectiveness of those formulas. Finally, the corresponding design procedure extracted from the formulas will be further addressed through a design example. View full abstract»

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  • A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers

    Page(s): 653 - 657
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB) |  | HTML iconHTML  

    A band-selective low-noise amplifier (BS-LNA) for multiband orthogonal frequency-division multiplexing ultra-wide-band (UWB) receivers is presented. A switched capacitive network that controls the resonant frequency of the LC load for the band selection is used. It greatly enhances the gain and noise performance of the LNA in each frequency band without increasing power consumption. Moreover, a fully differential configuration is employed to suppress the common-mode switching noise that is generated during the band transition interval. Fabricated in a 0.18-mum CMOS process, the BS-LNA achieves a peak power gain of 16 dB, a minimum noise figure of 2.74 dB, and an third-order input intercept point of -8.8 dBm at a current consumption of 7.95 mA from a 1.5-V supply. Little performance degradation is observed when the current consumption is reduced by half. The experimental results also show a worst-case band-switching time of less than 3.4 ns, with a peak switching noise voltage of less than 70 muV at the output. View full abstract»

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  • Low-Power Short-Range Radio CMOS Subharmonic RF Front-End Using CG-CS LNA

    Page(s): 658 - 662
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (430 KB) |  | HTML iconHTML  

    A 2.4-GHz fully integrated differential RF front-end was designed and implemented using 0.18-mum CMOS process. This design was targeted for low-power and low-cost applications such as short-range radio in biomedical devices. This RF front-end consists of a common-gate common-source low-noise-amplifier, a frequency doubler passive subharmonic mixer, and a resistive source degeneration intermediate frequency buffer. It consumes 2.5 mA from a 1.8-V supply. It occupies 950 mum times500 mum active area, which is only approximately 30% of that of the conventional RF front-end. This subharmonic RF front-end achieves 26-dB conversion gain, 9-dB noise figure and -10-dBm IIP3. View full abstract»

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  • A Low-Jitter Polyphase-Filter-Based Frequency Multiplier With Phase Error Calibration

    Page(s): 663 - 667
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (802 KB) |  | HTML iconHTML  

    A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static phase error of the calibration circuit is 2.4 ps. The calibration leads to the normalized rms jitter of 0.049%. View full abstract»

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  • A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS

    Page(s): 668 - 672
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (821 KB) |  | HTML iconHTML  

    We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5-bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply. View full abstract»

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  • A Low-Power Implementation of Asynchronous 8051 Employing Adaptive Pipeline Structure

    Page(s): 673 - 677
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (525 KB) |  | HTML iconHTML  

    This paper presents a low-power implementation of the A8051 processor. It employs an adaptive pipeline structure that allows to skip a redundant stage operation and to combine with the neighboring empty stage. The processor has three features to reduce the power dissipation as well as to improve performance: multilooping control for multicycle instructions, branch predictor for unconditional branches, and a single threading in the EXE stage. The experimental results show that A8051 runs about 1.8 times faster than the synchronous counterpart, CIP51 [reported in the HC8051F0xx Family Datasheet (2002)]. In terms of Et2 , our implementation shows 15 times higher efficiency than that of asynchronous counterpart developed by the Nanyang University [Chang and Gwee (2006)]. View full abstract»

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  • Sandberg's Representation Theorem and Classification of Linear Systems

    Page(s): 678 - 679
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (72 KB) |  | HTML iconHTML  

    It is shown that the theorem on representation of linear time-invariant system input-output maps recently published by Sandberg can be used to formulate an interesting classification of the known linear system maps. A certain property of a system map defined in this theorem and closely related to the notion of approximately-finite or vanishing memory can be also used as the system classifier. Restricting in it to consideration of only causal systems, we can distinguish between three cases: systems with no memory, with vanishing memory, and with infinitely long memory. Each of these cases is specific with regard to possessing or not possessing its own representation. View full abstract»

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  • Improving the Security of Chaotic Synchronization With a \Delta -Modulated Cryptographic Technique

    Page(s): 680 - 684
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    A secure chaos-based communication with a Delta-modulated chaotic cryptographic technique is developed in this paper. We prove that a Delta-modulated feedback control of a 1-D discrete- time control system gives rise to a chaotic system. Base on this chaotic system, a modified parameter modulation scheme is proposed to improve security. As illustrated by numerical simulation, the parameter in the sender is protected by a secure cryptosystem against two popular attacks. View full abstract»

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  • Improved Bounds on the L(2,1) -Number of Direct and Strong Products of Graphs

    Page(s): 685 - 689
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (179 KB) |  | HTML iconHTML  

    The frequency assignment problem is to assign a frequency which is a nonnegative integer to each radio transmitter so that interfering transmitters are assigned frequencies whose separation is not in a set of disallowed separations. This frequency assignment problem can be modelled with vertex labelings of graphs. An L(2,1)-labeling of a graph G is a function f from the vertex set V(G) to the set of all nonnegative integers such that |f(x)-f(y)| ges 2 if d(x,y)=1 and |f(x)-f(y)| ges 1 if d(x,y)=2 , where d(x,y) denotes the distance between x and y in G. The L(2,1) -labeling number lambda(G) of G is the smallest number k such that G has an L(2,1)-labeling with max{f(v):v isin V(G)}=k. This paper considers the graph formed by the direct product and the strong product of two graphs and gets better bounds than those of Klavzar and Spacapan with refined approaches. View full abstract»

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  • Improved Free-Weighting Matrix Approach for Stability Analysis of Discrete-Time Recurrent Neural Networks With Time-Varying Delay

    Page(s): 690 - 694
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (150 KB) |  | HTML iconHTML  

    This paper deals with the problem of exponential stability for a class of discrete-time recurrent neural networks with time-varying delay by employing an improved free-weighting matrix approach. The relationship among the time-varying delay, its upper bound and their difference is taken into account. As a result, a new and less conservative delay-dependent stability criterion is obtained without ignoring any useful terms on the difference of a Lyapunov function, which is expressed in terms of linear matrix inequalities. Finally, numerical examples are given to demonstrate the effectiveness of the proposed techniques. View full abstract»

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  • Optimal Filtering for Systems With Multiple Packet Dropouts

    Page(s): 695 - 699
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (191 KB) |  | HTML iconHTML  

    This paper is concerned with the optimal filtering problem for discrete-time stochastic linear systems with multiple packet dropouts, where the number of consecutive packet dropouts is limited by a known upper bound. Without resorting to state augmentation, the system is converted to one with measurement delays and a moving average (MV) colored measurement noise. An unbiased optimal filter is developed in the linear least-mean-square sense. Its solution depends on the recursion of a Riccati equation and a Lyapunov equation. A numerical example shows the effectiveness of the proposed filter. View full abstract»

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  • A Gaussian Approximation of High-Order Distortion Spectrum in Broadband Amplifiers

    Page(s): 700 - 704
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (218 KB) |  | HTML iconHTML  

    A novel analytical Gaussian approximation is developed for the evaluation of the distortion spectrum introduced by a nonlinear amplifier. This method allows to consider high-order distortion contributions when the device is driven by a broadband signal with Gaussian amplitude distribution. The results are applied to a ninth-order power series model based on well known single-tone and two-tone analysis parameters. The cascade of two or more amplifiers is investigated as well providing a complete set of tools for the early system specification of broadband transceivers. Simulations shows excellent agreement even for high input power levels, when former third-order and fifth-order approximations fail to yield accurate predictions. View full abstract»

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  • An FPGA Implementation of MML-DFE for Spatially Multiplexed MIMO Systems

    Page(s): 705 - 709
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    Although the maximum-likelihood decision-feedback equalization (ML-DFE) detection method for multi-input multi- output (MIMO) system leads to a good compromise between the performance and the complexity, the computational complexity of the ML part in the ML-DFE is still large. This paper describes a modified maximum-likelihood (MML) algorithm, which reduces the computational complexity of the original ML algorithm significantly without degrading the performance. Then, based on the MML algorithm, we propose the MML-DFE, which has the same performance as the ML-DFE but has much lower complexity. Both the ML-DFE block and MML-DFE block for 4times4 MIMO system have been implemented in field-programmable gate array to verify the functional correctness and the complexity advantage. View full abstract»

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  • Comments on "Improved Sufficient Conditions for Global Asymptotic Stability of Delayed Neural Networks

    Page(s): 710
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    In this note, we point out that the results given in the paper by Wu and Cui (2007) can be obtained by using the results given in Lu (2003). Moreover, the results given in the second paper are much stronger under less restrictive conditions. View full abstract»

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  • Special Issue on: Circuits and Systems Solutions for Nanoscale CMOS Design Challenges

    Page(s): 711
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope