# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

## Filter Results

Displaying Results 1 - 22 of 22

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

Publication Year: 2008, Page(s): C2
| |PDF (42 KB)
• ### A Robust Mixed-Size Legalization and Detailed Placement Algorithm

Publication Year: 2008, Page(s):1349 - 1362
Cited by:  Papers (14)
| |PDF (795 KB) | HTML

Placement is one of the most important steps in the RTL-to-GDSII synthesis process as it directly defines the interconnects. The rapid increase in IC design complexity and the widespread use of intellectual-property blocks have made the so-called mixed-size placement a very important topic in recent years. The contributions of this paper include the following: 1) It proposes a flexible and robust ... View full abstract»

• ### An Efficient Graph-Based Algorithm for ESD Current Path Analysis

Publication Year: 2008, Page(s):1363 - 1375
Cited by:  Papers (3)
| |PDF (1099 KB) | HTML

The electrostatic discharge (ESD) problem has become a challenging reliability issue in nanometer-circuit design. High voltages that resulted from ESD might cause high current densities in a small device and burn it out, so on-chip protection circuits for IC pads are required. To reduce the design cost, the protection circuit should be added only for the IC pads with an ESD current path, which cau... View full abstract»

• ### A Randomized Greedy Method for Rectangular-Pattern Fill Problems

Publication Year: 2008, Page(s):1376 - 1384
Cited by:  Papers (3)
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In this paper, a class of problems of physical-design optimization with rectangular shapes is presented. Efficient solutions for this class of optimization problems are needed for rectangular metal fill/negative-fill insertion during postrouting optimization. These problems are also shown to be closely related to the problem of floorplanning with rectangular macrocells. The solution must satisfy c... View full abstract»

• ### Robust Clock Tree Routing in the Presence of Process Variations

Publication Year: 2008, Page(s):1385 - 1397
Cited by:  Papers (9)
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Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock skew still limits post-manufacturing performance. Process-induced skew presents an ever-growing limitation for high-speed large-area clock networks. To achieve multigigahertz operation for high-end designs, clock networks must be co... View full abstract»

• ### Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model

Publication Year: 2008, Page(s):1398 - 1411
Cited by:  Papers (62)
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The force-directed quadratic placer ldquoKraftwerk2,rdquo as described in this paper, is based on two main concepts. First, the force that is necessary to distribute the modules on the chip is separated into the following two components: a hold force and a move force. Both components are implemented in a systematic manner. Consequently, Kraftwerk2 converges such that the module overlap is reduced ... View full abstract»

• ### Static Analysis of Transaction-Level Communication Models

Publication Year: 2008, Page(s):1412 - 1424
Cited by:  Papers (1)
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We propose a methodology for the early estimation of communication implementation choice effects, starting from an abstract transaction-level system model (TLM). The reference version of the TLM considered is the Open SystemC initiative library. The methodology is based on the computation of metrics that abstract useful information from the initial system model. The metrics are precisely defined u... View full abstract»

• ### Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures

Publication Year: 2008, Page(s):1425 - 1438
Cited by:  Papers (15)
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This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements of the target device. The optimization objectives include power consumption and resource usage. This paper presents a two-stage synthesis approach consisting of the following: (1) core to router mapping and (2) custom topology and route gener... View full abstract»

• ### Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications

Publication Year: 2008, Page(s):1439 - 1452
Cited by:  Papers (12)
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As technology advances, it becomes feasible to implement a large multiprocessor systems-on-chip (MPSoCs) to satisfy the increased performance demands of embedded applications. The increased complexity of systems leads to an increased power consumption. Reducing the consumption is an important task, considering that the available power may be limited in battery-operated embedded systems. The select... View full abstract»

• ### Isolation Techniques for Soft Cores

Publication Year: 2008, Page(s):1453 - 1466
Cited by:  Papers (2)  |  Patents (3)
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A cost effective system-on-a-chip (SOC) test strongly hinges on the parallel independent test of SOC cores, which can only be ensured through proper core isolation techniques. Whereas a core isolation mechanism can provide controllability and observability at the core I/O interface, its implementation may have various implications on area, functional timing, test time and data volume, and at-speed... View full abstract»

• ### Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time

Publication Year: 2008, Page(s):1467 - 1478
Cited by:  Papers (38)
| |PDF (774 KB) | HTML

Dynamic voltage and frequency scaling can save energy for real-time systems. Frequencies are generally assumed proportional to voltages. Previous studies consider the probabilistic distributions of tasks' execution time to assist dynamic voltage scaling in task scheduling. These studies use probability information for intratask voltage scheduling but do not sufficiently explore the opportunities f... View full abstract»

• ### Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management

Publication Year: 2008, Page(s):1479 - 1492
Cited by:  Papers (75)  |  Patents (7)
| |PDF (701 KB) | HTML

Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked high-power density layers of 3D CMPs increase the importance and difficulty of thermal management. In this paper, we investigate the 3D CMP run-time thermal management problem and describe efficient management techniques. This paper... View full abstract»

• ### A Fast Exploration Procedure for Analog High-Level Specification Translation

Publication Year: 2008, Page(s):1493 - 1497
Cited by:  Papers (4)
| |PDF (240 KB) | HTML

This paper presents an exploration procedure for mapping given functional specifications of an analog system to the specification parameters of individual component blocks of the system topology. A meet-in-the-middle approach has been followed for constructing the feasible design space. It is constructed as the intersection of an application-bounded specification space and a circuit-realizable spe... View full abstract»

• ### Dual-$V_{dd}$ Buffer Insertion for Power Reduction

Publication Year: 2008, Page(s):1498 - 1502
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This paper presents the first in-depth study on dual-Vdd buffer insertion for power minimization under delay constraint. Compared with delay-optimal single Vdd buffer insertion, the dual- Vdd buffer insertion reduces power by 16%. Such power reduction increases when the delay specification is relaxed. Whereas the van Ginneken algorithm can be extended to handle the new problem... View full abstract»

• ### Self-Adaptive Data Caches for Soft-Error Reliability

Publication Year: 2008, Page(s):1503 - 1507
Cited by:  Papers (7)  |  Patents (2)
| |PDF (358 KB) | HTML

Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and transistor budget, protecting them against soft errors is of paramount importance. Recent research has focused on the design of cost-effective reliable data caches in terms of performance, energy, and area overheads, based on t... View full abstract»

• ### Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method

Publication Year: 2008, Page(s):1508 - 1513
Cited by:  Papers (5)
| |PDF (525 KB) | HTML

An efficient method based on a direct boundary element method is proposed for extracting frequency-dependent substrate coupling parameters. A frequency-independent real-valued linear equation system is first solved. Then, the solution is transformed into frequency-dependent parameters at a specified frequency with the Sherman-Morrison-Woodbury formula. The first step is performed only once for a g... View full abstract»

• ### Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking

Publication Year: 2008, Page(s):1513 - 1517
Cited by:  Papers (3)
| |PDF (218 KB) | HTML

This paper presents a lightweight interval analysis technique for determining the lower and upper bounds for program variables and its application in improving software model checking techniques. The experiments demonstrate that it is an effective approach to alleviate the state explosion problem in software model checking. View full abstract»

• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

Publication Year: 2008, Page(s): 1518
| |PDF (25 KB)

Publication Year: 2008, Page(s): 1519
| |PDF (291 KB)

Publication Year: 2008, Page(s): 1520
| |PDF (269 KB)
• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

Publication Year: 2008, Page(s): C3
| |PDF (27 KB)

## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu