# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 42

Publication Year: 2008, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2008, Page(s): C2
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• ### Photodiode Peripheral Utilization Effect on CMOS APS Pixel Performance

Publication Year: 2008, Page(s):1405 - 1411
Cited by:  Papers (6)
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A photodiode (PD)-type CMOS active pixel sensor (APS) pixel is comprised of a reverse-biased p-n-junction diode (PD) for photon conversion and charge storage, and a number of MOS transistors. Junction capacitance of the PD has two major components; bottom plate (area) and side wall (periphery). Both play important roles in the electro-optical performance of PD-APS pixels. This paper reports PD per... View full abstract»

• ### Power and area-efficient adaptive equalization at microwave frequencies

Publication Year: 2008, Page(s):1412 - 1420
Cited by:  Papers (6)
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We present a low power analog adaptive equalization technique suitable for combating inter-symbol-interference at very high data rates. The proposed technique, which we term the lumped parameter equalizer, addresses several of the problems associated with conventional microwave equalizers based on the tapped delay line structure. The theory is given, and simulation results comparing it with the pe... View full abstract»

• ### On the Evaluation of the Exact Output of a Switched Continuous-Time Filter and Applications

Publication Year: 2008, Page(s):1421 - 1429
Cited by:  Papers (1)
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In this paper, a study of the operation of switched continuous-time filters (SCTFs), defined as continuous-time filters with elements that are alternatively switched on and off in the signal path, is conducted. A well-known example is the use of switched resistors to multiply their value, but the universe of applications is wider. First, a detailed calculation of the output of an SCTF in the frequ... View full abstract»

• ### An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit

Publication Year: 2008, Page(s):1430 - 1440
Cited by:  Papers (32)
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This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H) circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes the operational amplifier (opamp) gain, slew rate, bandwidth, and capacitor-matching requirements in ... View full abstract»

• ### Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

Publication Year: 2008, Page(s):1441 - 1454
Cited by:  Papers (103)  |  Patents (1)
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The need for highly integrable and programmable analog-to-digital converters (ADCs) is pushing towards the use of dynamic regenerative comparators to maximize speed, power efficiency and reconfigurability. Comparator thermal noise is, however, a limiting factor for the achievable resolution of several ADC architectures with scaled supply voltages. While mismatch in these comparators can be compens... View full abstract»

• ### A Heterogeneous 16-Bit DAC Using a Replica Compensation

Publication Year: 2008, Page(s):1455 - 1463
Cited by:  Papers (4)
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A highly monotonic very low power 16-bit 2-MS/s digital-to-analog converter (DAC) for high-resolution control loop systems is proposed and demonstrated. Replica compensation is used in improving the monotonicity of a heterogeneous DAC composed of a coarse current steering DAC and a fine resistor-ladder DAC. A complete DAC, including an on-chip bandgap reference and an output buffer, consumes only ... View full abstract»

• ### A Truly Low-Cost High-Efficiency ASK Demodulator Based on Self-Sampling Scheme for Bioimplantable Applications

Publication Year: 2008, Page(s):1464 - 1477
Cited by:  Papers (28)
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In the fields of wireless bioelectronics implants and sensor network systems, amplitude shift keying (ASK) is one of the most commonly used schemes employed to modulate the baseband signal with reference to the intermediate or even the carrier frequency. In this study, a demodulator architecture capable of dealing with most of the previous limitations in an ASK-utilized medical implant, especially... View full abstract»

• ### A Novel BPSK Demodulator for Biological Implants

Publication Year: 2008, Page(s):1478 - 1484
Cited by:  Papers (30)
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A novel binary phase-shift keying (BPSK) demodulator architecture is presented. The design employs a phase frequency detector based phase-locked loop allowing for robust performance compared to prior art. Two different circuit implementations for the novel demodulator architecture are proposed. Based on theoretical analysis, the maximum data rate of the demodulator is derived to be 1/8th of the ca... View full abstract»

• ### Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line

Publication Year: 2008, Page(s):1485 - 1494
Cited by:  Papers (44)
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Power consumption in match lines is the most critical issue for low-power ternary content-addressable memory (TCAM) designs. In the proposed match-line architecture, the match line in each TCAM word is partitioned into four segments and is selectively pre-charged to reduce the match-line power consumption. The partially charged match lines are evaluated to determine the final comparison result by ... View full abstract»

• ### Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications

Publication Year: 2008, Page(s):1495 - 1501
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This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of 27 -1, 210 -1, 215 -1, 2 23 -1, and 231 -1 b according to CCITT recommendations, and the random word... View full abstract»

• ### Fast Sign Detection for RNS $(2^{n}-1,2^{n},2^{n}+1)$

Publication Year: 2008, Page(s):1502 - 1511
Cited by:  Papers (21)
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In this paper, we propose a fast algorithm for sign-extraction of a number given in the Residue Number System (2n-1,2n,2n+1) . The algorithm can be implemented using three n-bit wide additions, two of which can be done in parallel. It can be used in a wide variety of problems, i.e., in algorithms for dividing numbers in the RNS, or in evaluating the sign of ... View full abstract»

• ### Robust Optical Time-of-Flight Range Imaging Based on Smart Pixel Structures

Publication Year: 2008, Page(s):1512 - 1525
Cited by:  Papers (42)  |  Patents (4)
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The reliable detection of the three-dimensional position of arbitrary objects in a scene is a key capability of most animals and one of the most important tasks in machine vision. Today's preferred technical solution is optical time-of-flight (TOF) range imaging, due to its simplicity, its distance resolution, its large and adaptable measurement range, as well as the absence of shadowing problems.... View full abstract»

• ### A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video

Publication Year: 2008, Page(s):1526 - 1535
Cited by:  Papers (42)
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Motion estimation (ME) in high-definition H.264 video coding presents a significant design challenge for memory bandwidth, latency, and cost because of its large search range and various modes. To conquer this problem, this paper presents a low-latency and hardware-efficient ME design with three design techniques. The first technique on integer-pel ME (IME) adopts parallel instead of serial multir... View full abstract»

• ### An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters

Publication Year: 2008, Page(s):1536 - 1545
Cited by:  Papers (51)  |  Patents (2)
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A novel algorithm for designing low-power and hardware-efficient linear-phase finite-impulse response (FIR) filters is presented. The algorithm finds filter coefficients with reduced number of signed-power-of-two (SPT) terms given the filter frequency response characteristics. The algorithm is a branch-and-bound-based algorithm that fixes a coefficient to a certain value. The value is determined b... View full abstract»

• ### A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters

Publication Year: 2008, Page(s):1546 - 1559
Cited by:  Papers (9)
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A massively parallel systolic-array architecture is proposed for the implementation of real-time VLSI spatio-temporal 3-D IIR frequency-planar filters at a throughput of one-frame-per-clock-cycle (OFPCC). The architecture is based on a differential-form transfer function and is of low circuit complexity compared with the direct-form architecture. A 3-D look-ahead (LA) form of the transfer function... View full abstract»

• ### Optimal Design of Frequency-Response Masking Filters With Reduced Group Delays

Publication Year: 2008, Page(s):1560 - 1570
Cited by:  Papers (10)
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In this paper, a new method for the design of optimal finite-impulse response frequency-response masking (FRM) filters with reduced passband group delays is proposed. To meet the prescribed magnitude response and group delay, the proposed design method takes into account both the magnitude error and the group delay error. The key step is the derivation of the group delay and its gradient with resp... View full abstract»

• ### Blind-Channel Identification for MIMO Single-Carrier Zero-Padding Block-Transmission Systems

Publication Year: 2008, Page(s):1571 - 1579
Cited by:  Papers (17)  |  Patents (1)
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We propose a blind identification method for multiple-input multiple-output (MIMO) single-carrier zero-padding block-transmission systems. The method uses periodic precoding on the source signal before transmission. The estimation of the channel impulse response matrix consists of two steps: 1) obtain the channel product matrix by solving a lower-triangular linear system; 2) obtain the channel imp... View full abstract»

• ### ETHFB: A New Class of Even-Length Biorthogonal Wavelet Filters for Hilbert Pair Design

Publication Year: 2008, Page(s):1580 - 1588
Cited by:  Papers (10)
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A new class of biorthogonal filter banks, called the even-triplet-halfband-filter-bank (ETHFB), is introduced here. The filters are of even length and have linear phase response. There are two versions of the ETHFB, and they are modifications of the (odd-length) triplet-halfband-filter-bank. The parametric Bernstein polynomial is utilized in the construction of the three kernels that define the ET... View full abstract»

• ### A Generalized Reverse Block Jacket Transform

Publication Year: 2008, Page(s):1589 - 1600
Cited by:  Papers (25)  |  Patents (3)
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Jacket matrices motivated by the center weight Hadamard matrices have played important roles in signal processing, communication, image compression, cryptography, etc. In this paper we propose a notation called block Jacket matrix which substitutes elements of the matrix into common matrices or even block matrices. Employing the well-known Pauli matrices which are very important in many subjects, ... View full abstract»

• ### An Unconstrained Architecture for Systematic Design of Higher Order $SigmaDelta$ Force-Feedback Loops

Publication Year: 2008, Page(s):1601 - 1614
Cited by:  Papers (23)  |  Patents (1)
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Nowadays, SigmaDelta-modulation is a widely used technique for analog-to-digital (A/D) conversion, especially when aiming for high resolutions. While being applied initially for purely electrical A/D converters, its application has been expanded to mixed mechanical-electrical systems. This has led to the use of SigmaDelta force-feedback for digital readout of high-performance inertial sensors. How... View full abstract»

• ### Algorithmic ADC Offset Compensation by Nonwhite Data Chopping: System Model and Basic Theoretical Results

Publication Year: 2008, Page(s):1615 - 1627
Cited by:  Papers (3)
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This paper is devoted to show the impact of nonwhite chopping on the offset compensation in time-interleaved analog-to-digital converters. We develop a theoretical framework allowing the selection of optimal chopping sequences. We show that, on the one hand, the adoption of these (generally nonwhite) sequences allows to achieve faster offset compensation (thus increasing the signal-to-noise ratio)... View full abstract»

• ### Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs

Publication Year: 2008, Page(s):1628 - 1638
Cited by:  Papers (10)
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This paper presents a modular and comprehensive nonlinear time-domain behavioral model for phase-locked loops (PLLs) that are suitable for analyzing the impact on the output signal of the noise contribution and nonidealities of the constituent building blocks. The model building blocks are described by Simulink submodels and can be configured to implement different PLL topologies. Postprocessing o... View full abstract»

• ### A Spur Elimination Technique for Phase Interpolation-Based Fractional-$N$ PLLs

Publication Year: 2008, Page(s):1639 - 1647
Cited by:  Papers (14)  |  Patents (5)
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A fractional spur elimination technique that enables wide-bandwidth phase interpolation-based fractional-N phase-locked loops (PLLs) is proposed. The technique uses specially filtered dither to eliminate the spurious tones otherwise caused by inevitable phase errors. The design of a wide-bandwidth fractional-N PLL based on the spur elimination technique and a theoretical proof of the... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK