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Solid-State Circuits, IEEE Journal of

Issue 7 • Date July 2008

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Displaying Results 1 - 25 of 27
  • Table of contents

    Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits publication information

    Page(s): C2
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    Freely Available from IEEE
  • Table of contents

    Page(s): 1505 - 1506
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  • Introduction to the Special Issue on the 33rd European Solid-State Circuits Conference (ESSCIRC 2007)

    Page(s): 1507 - 1510
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    Freely Available from IEEE
  • A 1 V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications

    Page(s): 1511 - 1521
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    This paper presents a 1 V RF transceiver for biotelemetry and wireless body sensor network (WBSN) applications, realized as part of an ultra low power system-on-chip (SoC), the Sensiumtrade. The transceiver utilizes FSK/GFSK modulation at a data rate of 50 kbit/s to provide wireless connectivity between target sensor nodes and a central base-station node in a single-hop star network topology operating in the 862-870 MHz European short-range-device (SRD) and the 902-928 MHz North American Industrial, Scientific & Medical (ISM) frequency bands. Controlled by a proprietary media access controller (MAC) which is hardware implemented on chip, the transceiver operates half-duplex, achieving -102 dBm receiver input sensitivity (for 1E-3 raw bit error rate) and up to -7 dBm transmitter output power through a single antenna port. It consumes 2.1 mA during receive and up to 2.6 mA during transmit from a 0.9 to 1.5 V supply. It is fabricated in a 0.13 mum CMOS technology and occupies 7 mm2 in a SoC die size of 4 times 4 mm2. View full abstract»

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  • A 65 nm CMOS Multistandard, Multiband TV Tuner for Mobile and Multimedia Applications

    Page(s): 1522 - 1533
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    This paper presents a direct conversion, multistandard TV tuner implemented on a 65 nm digital CMOS process occupying less than 7 . The tuner is compliant with several digital terrestrial, fixed and mobile TV standards, including DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB noise figure at VHF, UHF, and L-band, respectively, while the measured sensitivity at UHF for the QPSK-frac12 DVB-T mode is at the PCB connector. The implemented RF front-ends support both single-ended and differential inputs. An integrated - fractional-N synthesizer operating from 1.2 to 1.8 GHz achieves less than 1 integrated phase error, thus enabling a maximum SNR in excess of 37 dB for VHF and UHF. Multistandard capability is also enabled by programmable channel-select filters. Power consumption is less than 140 mW in DVB-T mode for all three bands. View full abstract»

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  • A CMOS 5 nV /\surd Hz 74-dB-Gain-Range 82-dB-DR Multistandard Baseband Chain for Bluetooth, UMTS, and WLAN

    Page(s): 1534 - 1541
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    An analog baseband chain for a multistandard (Bluetooth, WCDMA/UMTS, and WLAN) reconfigurable receiver in a 0.13 mum CMOS occupying 1.65 mm2 is presented. The circuit consists of an open-loop programmable-gain amplifier (PGA1), an active-Gm-RC low-pass filter (LPF), and a closed-loop programmable-gain amplifier (PGA2). The chain gain can be programmed in the range -6 divide 68 dB, while the input-referred noise (IRN) is 5 nV/radicHz. A dynamic range (DR) larger than 82 dB is achieved for a 1% total harmonic distortion (THD). The current consumption is minimized and adjusted for the different operation conditions, down to 11 mA for the full chain. View full abstract»

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  • A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS

    Page(s): 1542 - 1552
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    This paper presents an integrated LNA for millimeter-wave applications implemented in 90 nm CMOS technology. Modeling methodology based solely on electromagnetic simulations, RC parasitic extraction and device measurements up to 20 GHz allows for ldquocorrect-by-constructionrdquo design at mm-wave frequencies and first-pass silicon success. The dual-stage cascode LNA has a peak gain of 15.5 dB at 64 GHz with a NF of 6.5 dB, while drawing 26mA per stage from 1.65 V. Output is 3.8 dBm. At , each stage draws 19 mA, with a peak gain and a NF of 13.5 dB and 6.7 dB, respectively. Measured results are in excellent agreement with simulations, proving the effectiveness of the proposed design methodology. A custom set-up for mm-wave NF measurement is also extensively described in the paper. View full abstract»

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  • A Wideband Millimeter-Wave Power Amplifier With 20 dB Linear Power Gain and +8 dBm Maximum Saturated Output Power

    Page(s): 1553 - 1562
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    A millimeter-wave power amplifier fabricated in 90 nm bulk CMOS technology consists of 3 identical cascode stages and on-chip matching networks (inter-stage, input, and output) implemented with wide-gap coplanar waveguides and M6-M5 (MIM) capacitors. The amplifier realizes a linear power gain of 19.7 dB at 52.4 GHz and 10.3 dB at 60 GHz. Maximum saturated output power and output-referred compression point are and 3.1 dBm, respectively. Peak PAE is 4.2%. The 1.180.96 die consumes 75 mA when operating from a 2 V supply. View full abstract»

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  • An Assessment of µ-Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration

    Page(s): 1563 - 1576
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    Single-grain (SG) thin-film transistors (TFTs) fabricated inside location-controlled silicon grains using the mu-Czochralski method are benchmarked for analog and RF applications. Each silicon grain is defined by excimer laser recrystallization of polysilicon. Thin-film transistors may be fabricated in this manner on silicon or low-cost flexible plastic substrates as processing temperatures remain below 350degC, making the SG-TFT a potential enabling technology for large-area highly integrated electronic systems or systems-in-package with low manufacturing cost. Operational amplifier and voltage reference circuits of varying complexity were designed and measured in order to evaluate the effects of channel position and processing variation on analog circuits. A two-stage telescopic cascode operational amplifier fabricated in an experimental 1.5 mum SG-TFT technology demonstrates a DC gain of 55 dB (unity-gain bandwidth of 6.3 MHz), while a prototype CMOS voltage reference with a power supply rejection ratio (PSRR) of 50 dB is also demonstrated. With fT comparable to single-crystal MOSFETs of comparable gate length, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with on-chip inductors and operating in the 433 MHz ISM band is demonstrated. Excellent agreement with simulations is attained using a modified BSIM-SOI model extracted from measurements of experimental SG-TFT devices. View full abstract»

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  • A Wide DR and Linear Response CMOS Image Sensor With Three Photocurrent Integrations in Photodiodes, Lateral Overflow Capacitors, and Column Capacitors

    Page(s): 1577 - 1587
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    A 1/3-inch, 800H x 600v pixels, 5.6 x 5.6 mum2 color CMOS image sensor with three photocurrent integrations in pixel photodiodes, pixel lateral overflow capacitors and column capacitors fabricated in a 0.18 mum 2P3M CMOS technology has been reported. The image sensor operates using photodiode integrations and lateral overflow integrations in low light condition and achieves a wide dynamic range (DR) performance of around 100 dB in its one exposure. The wide DR performance in one exposure makes high S/N ratios at the signal switching points in the multiple exposures. The CMOS image sensor also operates using the column capacitor integration in very bright light condition. In the column capacitor integration, the photocurrents generated at the photodiodes are directly integrated at the column capacitors in each column line. The combination of two exposures using the photodiode integrations and the lateral overflow integrations and one exposure using the column capacitors leads to the whole linear photo-electric conversion responses from low light to very bright light region. The fabricated image sensor achieves a high S/N ratio, a fully linear response and over 180 dB DR in the incident light ranging from about 1.4 x 10-2 lx to about 2.4 x 107 lx. View full abstract»

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  • Light Source Position Measurement Technique Applicable in SOI Technology

    Page(s): 1588 - 1593
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    Integrated optical sensors make use of a p-n-junction for light intensity detection, typically. Because of the costs, additional optical components are not available in standard integration processes. Therefore, in higher level optical sensors extra optical components are not part of an integration. In this paper a concept for integration is proposed, which especially allows to measure the angles of a far distance light source relative to the surface of the chip and the coordinate system of the integrated structure. The invention makes use of the stack topology and the light opacity of metal layers in the monolithic integration, the light translucency of , and the electrical light sensitivity of diodes. Because of perfect device isolation the implementation can be done most advantageously in SOI CMOS technology. With minor modifications it is applicable in other integration technologies as well. But leakage currents and device mismatching will limit the obtainable performance additionally. View full abstract»

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  • Time-of-Flight 3-D Imaging Pixel Structures in Standard CMOS Processes

    Page(s): 1594 - 1602
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    In this investigation we examine different pixel structures and readout principles to be used in imagers fabricated in standard CMOS processes, for example, the 0.5 and 0.35 processes available at the Fraunhofer IMS. The targeted applications are high-speed near-infra-red (NIR) 3-D imaging based on time-of-flight (TOF) measurements. We discuss various issues ranging from charge-coupling possibilities to noise, spectral responsivity and fill-factor, and present an extensive study of pixel configurations based on inverse biased p-n junction and MOS-C based photodetectors. We also discuss the possibilities of using a novel CMOS imaging pixel for TOF imaging applications: the charge-injection photogate (CI-PG) which presents parametric time-compression amplification. Finally, we compare and discuss all the pixel configurations examined. View full abstract»

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  • Interface Electronics for a CMOS Electrothermal Frequency-Locked-Loop

    Page(s): 1603 - 1608
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    This paper describes a new implementation of a CMOS electrothermal frequency-locked-loop (FLL), whose output frequency is determined by the temperature-dependent phase shift of an electrothermal filter (ETF). The FLL maintains a constant phase shift in the ETF, and as a result drives it with a signal whose frequency is a well-defined function of temperature. Compared to a previous implementation, the FLL described here has significantly more loop gain, less electrical phase-spread, and is more suitable for full integration. Measurements on 16 samples (from one batch) show that the temperature dependence of the FLL's output frequency agrees very well with the known thermal properties of bulk silicon. The untrimmed spread of this frequency is less than plusmn0.45% (3sigma) from -40degC to 100degC, which corresponds to a temperature-sensing inaccuracy of less than plusmn0.7degC (3sigma). View full abstract»

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  • Features and Design Constraints for an Optimized SC Front-End Circuit for Capacitive Sensors With a Wide Dynamic Range

    Page(s): 1609 - 1616
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    This paper presents optimization criteria for an integrated switched-capacitor front-end circuit for capacitive sensors with a wide dynamic range. The principle of the interface is based on the use of a relaxation oscillator. A negative-feedback circuit controls the charge-transfer speed to prevent the overload of the input amplifier for large input signals which thus enables a wide dynamic range of capacitor values. Moreover, it has been shown that the use of negative feedback can also result in much better noise performance. However, for the interface to function properly, there is a serious limitation for the value of a specific parasitic capacitance. Therefore, a method which extends the acceptable range of this parasitic capacitance is proposed. A novel method of linearity measurement which takes the influence of PCB parasitic capacitances into account, is also presented. The circuit has been designed and implemented in 0.7 mum standard CMOS technology. The supply voltage is 5 V and the measured value for the supply current is about 1.4 mA. Experimental results show that for the capacitor range of 1 pF to 300 pF, application of negative feedback yields a linearity of about 50 x10-6 (14 bits) with a 16-bit resolution for a measurement time of 100 ms. Tests have been performed over the temperature range from to . View full abstract»

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  • A Configurable High-Side/Low-Side Driver With Fast and Equalized Switching Delay

    Page(s): 1617 - 1625
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    A configurable high-side/low-side driver (HSD/LSD) for inductive loads is presented. The operating mode of this driver depends just upon external connection. The circuit incorporates improved protection circuitry using modified Zener diodes. These diodes are isolated, allowing large negative voltages at source and gate of the switch device. Drain-gate clamping turned out to be most suitable. Together with an isolated output stage of the driving circuit, this results in large negative source and gate voltages for the HSD configuration, leading to faster switch-off. After a qualitative description of the switching behavior, equations for the switching delay are derived which confirm fast and similar HSD/LSD switching times for the proposed driver. Experimental results in a 0.35 BiCMOS technology show that the gate can drop as low as in the high-side configuration. In the low-side configuration, the drain can rise as high as 45 V. Delay measurements for varying clamping levels and inductance values are presented. The configurable driver shows an excellent behavior both for high-side and low-side in an H-bridge motor driver. View full abstract»

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  • An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage

    Page(s): 1626 - 1637
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    A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 104 clock cycles. View full abstract»

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  • A High Bandwidth Power Scalable Sub-Sampling 10-Bit Pipelined ADC With Embedded Sample and Hold

    Page(s): 1638 - 1647
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    A pipelined ADC architecture for use in sub-sampled systems which is power scalable in relation to its down sampled bandwidth is presented. The ADC uses a technique to eliminate the front-end sample hold, thereby reducing power consumption. The technique allows for a power savings of 20% compared to a previous design. A method to improve the settling behavior of rapid power-on opamps is also presented. Measured results in a 1.8 V 0.18 CMOS process verify the removal of the front-end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With 50 MS/s, for the SNDR is 51.5 dB, and with 4.55 MS/s for the SNDR is 52.2 dB. View full abstract»

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  • 40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW

    Page(s): 1648 - 1656
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    A bandpass modulator with two time-interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40 MHz IF provide a signal band of 1 MHz with 72 DR and 65.1 dB peak SNR. The circuit, integrated in a 0.18 CMOS technology, uses a 60 MHz clock per channel. Experimental results show that the in-band region is not affected by tones caused by mismatches and that a two-tones input causes an IMD signal of 68 . The power consumption is 16 mW with 1.8 V supply. View full abstract»

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  • A Single-Die 124 dB Stereo Audio Delta-Sigma ADC With 111 dB THD

    Page(s): 1657 - 1665
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    This paper presents a highly power-efficient stereo delta-sigma ADC designed for high-precision applications, with measured inter-channel isolation over 130 dB. This design adopts a single-loop, fifth-order, 33 level analog modulator with positive and negative feedforward paths. An interpolated multilevel quantizer with unevenly weighted quantization levels replaces a conventional 5-bit flash type quantizer. These new techniques suppress signal dependent energy inside the delta-sigma loop, reduce internal channel coupling and power consumption. Manufactured in 0.35 mum double poly, three metal CMOS process, the single-die chip includes two analog modulators, on-chip bandgap reference circuit, decimation filter and serial interface circuits. The core die area is around 14.8 mm2. The ADC achieves 124 dB dynamic range (A-weighted), -111 dB THD over 20 kHz bandwidth. Total power consumption is less than 330 mW. View full abstract»

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  • A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion

    Page(s): 1666 - 1676
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    Time-to-digital converters (TDCs) are promising building blocks for the digitalization of mixed-signal functionality in ultra-deep-submicron CMOS technologies. A short survey on state-of-the-art TDCs is given. A high-resolution TDC with low latency and low dead-time is proposed, where a coarse time quantization derived from a differential inverter delay-line is locally interpolated with passive voltage dividers. This high-resolution TDC is monotonic by construction which makes the concept very robust against process variations. The feasibility is demonstrated by a 90 nm demonstrator which uses a 4x interpolation and provides a time domain resolution of 4.7 ps. An integral nonlinearity of 1.2 LSB and a differential nonlinearity of 0.6 LSB are achieved. The resolution restrictions imposed by an uncertainty of the stop signal and local variations are derived theoretically. View full abstract»

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  • A Flexible, Ultra-Low-Energy 35 pJ/Pulse Digital Back-End for a QAC IR-UWB Receiver

    Page(s): 1677 - 1687
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1290 KB) |  | HTML iconHTML  

    A low-energy, flexible digital back-end for the quadrature analog correlating (QAC) IR-UWB receiver, implemented in 0.13 m CMOS technology, is presented. The built-in flexibility allows the receiver to operate over a wide range of frequency bands, pulse rates, code lengths, acquisition modes, etc. This ability to dynamically trade power consumption, system performance and system reliability is crucial for application in sensor networks where energy is scarce. To avoid the large power penalty, that often accompanies the introduction of flexibility, the chip's architecture is based on nested FLEXmodules. These are small configurable modules with a local controller, that can be slowed down and clock gated individually. Communicating at 40 Mpulses/s, the resulting digital back-end consumes as little as 3.5 mW in acquisition mode and 1.5 mW during data reception. This is equivalent to an energy consumption of 35 pJ per received pulse. View full abstract»

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  • Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability

    Page(s): 1688 - 1698
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    Power switch transistors are very effective in cutting the leakage currents of digital circuits in a deep-freeze mode, by de-supplying unused blocks. Among existing power switch transistors, Super Cut-off CMOS (SCCMOS) is the most suited to a low supply voltage environment since it uses a low threshold voltage transistor. This power switch type achieves good leakage reduction results, provided that an optimal voltage is applied on its gate in order to maximize the leakage gain. This optimal voltage value, depending on the operating conditions (process, voltage, temperature), cannot be determined at the design level. A polarization circuit, that automatically finds the optimal bias voltage whatever the environment conditions, was therefore designed and fabricated. This circuit, made in Bulk 65 nm technology, achieves more than two decades leakage current reduction at the power switch level, for a power dissipation overhead of 45 nW at ambient temperature. A very simple scheme is also presented to alleviate the voltage stress applied on the dielectric in case of an ageing of the latter, increasing its time-to-breakdown by several orders of magnitude. View full abstract»

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  • Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

    Page(s): 1699 - 1710
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    This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized. View full abstract»

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  • ISSCC 2009 call for papers

    Page(s): 1711
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    Freely Available from IEEE

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan