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Electron Devices, IEEE Transactions on

Issue 7 • Date July 2008

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  • Table of contents

    Publication Year: 2008 , Page(s): C1 - C4
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  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2008 , Page(s): C2
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  • A Two-Step-Recess Process Based on Atomic-Layer Etching for High-Performance \hbox {In}_{0.52}\hbox {Al}_{0.48}\hbox {As}\hbox {/}\hbox {In}_{0.53} \hbox {Ga}_{0.47}\hbox {As} p-HEMTs

    Publication Year: 2008 , Page(s): 1577 - 1584
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1326 KB) |  | HTML iconHTML  

    We investigated 60-nm In0.52Al0.48As/In0.53Ga0.47As pseudomorphic high-electron mobility transistors (p-HEMTs) fabricated by using a Ne-based atomic-layer-etching (ALET) technology. The ALET process produced a reproducible etch rate of 1.47 Aring/cycle for an InP etch stop layer, an excellent InP etch selectivity of 70 against an In0.52Al0.48As barrier layer, and an rms surface-roughness value of 1.37 Aring for the exposed In0.52Al0.48As barrier after removing the InP etch stop layer. The application of the ALET technology for the gate recess of 60-nm In0.52Al0.48As/In0.53Ga0.47As p-HEMTs produced improved device parameters, including transconductance (GM), cutoff frequencies (fT)> and electron saturation velocity (vsat) in the channel layer, which is mainly due to the high etch selectivity and low plasma-induced damage to the gate area. The 60-nm In0.52Al0.48As/In0.53Ga0.47As p-HEMTs fabricated by using the ALET technology exhibited GM,Max = 1-17 S/mm, fT = 398 GHz, and vsat = 2.5 X 107 cm/s. View full abstract»

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  • Surface Acoustic Waves in Reverse-Biased AlGaN/GaN Heterostructures

    Publication Year: 2008 , Page(s): 1585 - 1591
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (442 KB) |  | HTML iconHTML  

    Properties of surface acoustic waves (SAWs) in reverse-biased AlGaN/GaN heterostructures on (0001) sapphire substrates were studied by examining the characteristics of SAW filters composed of interdigital Schottky and ohmic contacts. The fundamental and higher frequency SAW signals in measured -parameters were attributed to Rayleigh and Sezawa modes, respectively. The onsets of the SAW signals, which were close to the threshold voltage of HEMTs in the vicinities of the respective filters, changed in response to the spatial variation of the threshold voltage. The onset of Sezawa mode was deeper than that of Rayleigh mode, and the difference in onset was larger for longer SAW wavelengths. These results are possibly explained by the change of the input capacitance of interdigital transducers due to the reverse-bias voltages or by the difference in the distribution of SAW energy between the two modes. View full abstract»

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  • Investigation of High-Electric-Field Degradation Effects in AlGaN/GaN HEMTs

    Publication Year: 2008 , Page(s): 1592 - 1602
    Cited by:  Papers (35)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (427 KB) |  | HTML iconHTML  

    High-electric-field degradation phenomena are investigated in GaN-capped AlGaN/GaN HEMTs by comparing experimental data with numerical device simulations. Under power- and OFF-state conditions, 150-h DC stresses were carried out. Degradation effects characterizing both stress experiments were as follows: a drop in the dc drain current, the amplification of gate-lag effects, and a decrease in the reverse gate leakage current. Numerical simulations indicate that the simultaneous generation of surface (and/or barrier) and buffer traps can account for all of the aforementioned degradation modes. Experiments also showed that the power-state stress induced a drop in the transconductance at high gate-source voltages only, whereas the OFF-state stress led to a uniform transconductance drop over the entire gate-source-voltage range. This behavior can be reproduced by simulations provided that, under the power-state stress, traps are assumed to accumulate over a wide region extending laterally from the gate edge toward the drain contact, whereas, under the OFF-state stress, trap generation is supposed to take place in a narrower portion of the drain-access region close to the gate edge and to be accompanied by a significant degradation of the channel transport parameters. View full abstract»

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  • Methodology for Small-Signal Model Extraction of AlGaN HEMTs

    Publication Year: 2008 , Page(s): 1603 - 1613
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (905 KB) |  | HTML iconHTML  

    Both large- and small-periphery AlGaN high- electron mobility transistors (HEMTs) will find applications in microwave systems from 2 to 40 GHz because of their superior power handling capability. A self-consistent approach is presented for the linear model's parameter extraction from measured S-parameters. The model for parasitics is selected to reflect loading from both the probe pads and the interconnect regions, including the air bridges. The objective is to accurately extract intrinsic model parameters as the device periphery is increased from 50 mum to 1 mm and to isolate the effects of device layouts, including air bridging the source regions. To accurately extract the shunt and series parasitics, the device must be represented in its ON- and OFF-states determined by the gate and drain bias. The intrinsic device capacitances are not negligible in the forward and beyond-pinchoff reverse bias states at zero drain bias and must be accounted for. With these corrections to the measured S-parameters, consistent results for the intrinsic device parameters are obtained with both small- and large-periphery AlGaN HEMTs. View full abstract»

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  • Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

    Publication Year: 2008 , Page(s): 1614 - 1620
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1509 KB) |  | HTML iconHTML  

    A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability. View full abstract»

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  • Advanced Amorphous Silicon Thin-Film Transistors for AM-OLEDs: Electrical Performance and Stability

    Publication Year: 2008 , Page(s): 1621 - 1629
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (318 KB) |  | HTML iconHTML  

    We fabricated and characterized the advanced amorphous silicon thin-film transistors with a bilayer structure for both the active and gate dielectric films. The electrical field across the gate insulator has a significant influence on the device threshold voltage electrical stability. We show that high thin-film transistor stability can be achieved even under the presence of a high channel current. Its electrical and high-temperature stability improves up to a factor of five when the TFT biasing condition changes from the linear to the saturation region of operation. View full abstract»

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  • The Impact of Nitrogen Engineering in Silicon Oxynitride Gate Dielectric on Negative-Bias Temperature Instability of p-MOSFETs: A Study by Ultrafast On-The-Fly I_{\rm DLIN} Technique

    Publication Year: 2008 , Page(s): 1630 - 1638
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (473 KB) |  | HTML iconHTML  

    Degradation of p-MOSFET parameters during negative-bias temperature instability (NBTI) stress is studied for different nitridation conditions of the silicon oxynitride (SiON) gate dielectric, using a recently developed ultrafast on-the-fly IDLIN technique having 1-mus resolution. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is governed by nitrogen (N) density at the Si/SiON interface. The relative contribution of interface trap generation and hole trapping to overall degradation as varying interfacial N density is qualitatively discussed. Plasma oxynitride films having low interfacial N density show interface trap dominated degradation, whereas relative hole trapping contribution increases for thermal oxynitride films having high N density at the Si/SiON interface. View full abstract»

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  • Carrier Transportation Mechanism of the \hbox {TaN}/ \hbox {HfO}_{2}/\hbox {IL}/\hbox {Si} Structure With Silicon Surface Fluorine Implantation

    Publication Year: 2008 , Page(s): 1639 - 1646
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1311 KB) |  | HTML iconHTML  

    In this paper, the current transportation mechanism of HfO2 gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO2/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO2 barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HfOF conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO2 conduction band, which contributes to Frenkel-Poole conduction. View full abstract»

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  • Stress-Induced Positive Charge in Hf-Based Gate Dielectrics: Impact on Device Performance and a Framework for the Defect

    Publication Year: 2008 , Page(s): 1647 - 1656
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (455 KB) |  | HTML iconHTML  

    A Hf-based dielectric has been selected to replace SiON for CMOS technologies. When compared with SiON, Hf dielectrics can suffer from higher instability. Previous attentions were focused on electron trapping, and positive charging received less attention. The objective of this paper is to study the impact of positive charging on device performance and to provide a framework for the defect. Three components of threshold voltage instability Delta Vth are unambiguously identified for pMOSFETs, i.e., loop, loop-shift, and up-loop. The loop dominates Delta Vth at a relatively short time (< 1 s). After stressing for a longer time, the whole loop is shifted in the negative direction. Unlike the loop, the up-loop cannot readily be recharged after recovery. In addition to the generated interface states, three different types of positive charges are formed in the Hf-based stacks, i.e., cyclic positive charges (CPC), antineutralization positive charges (ANPC), and as-grown hole trapping (AHT). Each type of defect has its unique signatures and properties. CPC can repeatedly be charged and discharged by alternating the gate bias polarity. ANPC is more difficult to neutralize, whereas AHT is harder to charge. Both the generated interface states and the AHT saturate at longer stress time, but ANPC does not. ANPC reduces at higher measurement temperature, but CPC is insensitive to temperature. The relation between each type of defect and each component of Delta Vth is clarified. View full abstract»

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  • Methodology for Flatband Voltage Measurement in Fully Depleted Floating-Body FinFETs

    Publication Year: 2008 , Page(s): 1657 - 1663
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (314 KB) |  | HTML iconHTML  

    Among the novel methods for flatband voltage (Vfb) measurement, we demonstrate that a gate-leakage-based technique is the most suitable for measuring Vfb in floating-body MOSFETs with ultrathin gate dielectrics. Starting from carrier separation experiments on planar MOSFETs, we show the universality of the gate conduction mechanism dependence on band alignment for both n- and p-FETs. We demonstrate that metrics based on the gate leakage (either its valence-band electron-tunneling component or its first-order derivative) reflect this dependence and allow equivalent-oxide-thickness-independent Vfb quantification. This dependence is also valid for high-k and capped gate dielectrics, whereas their gate conduction mechanism is dominated by direct tunneling. To illustrate, we extract gate-leakage-derivative-based metrics and measure Vfb of TaN and TiN gate electrodes in multiple-fin FETs integrated on silicon-on-insulator. View full abstract»

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  • RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate

    Publication Year: 2008 , Page(s): 1664 - 1671
    Cited by:  Papers (16)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (503 KB) |  | HTML iconHTML  

    In this paper, we investigate the impact of a passivation layer on the performance of a commercial high-resistivity (HR) SOI CMOS technology. The passivation layer consists of a 300-nm-thick polysilicon cover located directly below the buried oxide (BOX). Both passive and active devices are studied. It is demonstrated that substrate passivation completely suppresses substrate losses that are usually induced by parasitic surface conduction at the substrate/BOX interface in oxidized HR Si substrates. We also report no effect of the underlying polysilicon on the dc and RF behavior of MOSFETs devices. The results shown here strongly suggest that substrate passivation using polysilicon is a promising tool to eradicate substrate losses in HR SOI wafers, thereby increasing the performance of functional SOI logic and high-speed circuits. View full abstract»

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  • A Compact Model of Phase-Change Memory Based on Rate Equations of Crystallization and Amorphization

    Publication Year: 2008 , Page(s): 1672 - 1681
    Cited by:  Papers (18)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (522 KB) |  | HTML iconHTML  

    In this paper, a compact model of phase-change memory based on the rate equations of crystallization and amorphization will be presented and confirmed by measurement. The model reproduces the nonlinear current-voltage behavior of both the "set" and "reset" states. Temperatures in the phase-change layer are calculated by a thermal equivalent circuit. The temperature-dependent crystallization and amorphization of the phase-change layer are taken into account in order to express resistance changes between the "set" and "reset" states. The crystallization rate is calculated based on the nucleation-growth model. The heat of fusion (the latent heat) is taken into account in the calculation of the amorphization rate. View full abstract»

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  • An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides

    Publication Year: 2008 , Page(s): 1682 - 1692
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (549 KB) |  | HTML iconHTML  

    In this paper, we present a completely analytical model for the gate tunneling current, which can be used to get a first-order estimate of this parameter in present-generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. The model has been developed from first principles, and it does not use any empirical fitting and/or correction parameters. It takes into account the quantization of the electron energy levels within the inversion layer of a MOSFET, which behaves similar to a potential well. Several interesting simplifications regarding this well structure have been made, and all these assumptions have been rigorously justified, both based on physical arguments as well as through numerical quantifications. An extremely interesting and important outcome of this procedure is a nonzero value of the wavefunction at the semiconductor-insulator interface, which is physically justified, however, contrary to what other existing literatures in this area assume. This procedure also led to a closed-form analytical expression for the inversion layer thickness. The interface wavefunction was used, in association with the tunneling probability through the gate oxide, and the carriers in transit model in the gate metal, to find the resultant gate tunneling current density as a function of the applied gate-to-body voltage. The results obtained from our simple and completely analytical model were compared with the experimental results reported in the literature, and the match is found to be excellent for varying oxide thicknesses and substrate doping concentrations, which justifies the authenticity of the model developed in this work here. View full abstract»

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  • Compact Layout and Bias-Dependent Base-Resistance Modeling for Advanced SiGe HBTs

    Publication Year: 2008 , Page(s): 1693 - 1701
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (858 KB) |  | HTML iconHTML  

    In this paper, an improved and extended set of physics-based analytical equations for describing the external and internal base resistance of silicon-germanium HBTs as a function of geometry (layout) is presented. The investigated layouts include single- and double-base contacts not only in parallel but also perpendicular to the emitter finger. In addition, via and slot base contacts, a large range of link to internal-base-sheet-resistance ratio, and changes in external base layout dimensions are covered. The new equations are verified using quasi-3-D device simulation and are demonstrated to be applicable to all practically useful emitter aspect ratios. View full abstract»

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  • Characterization of Distribution of Trap States in Silicon-on-Insulator Layers by Front-Gate Characteristics in n-Channel SOI MOSFETs

    Publication Year: 2008 , Page(s): 1702 - 1707
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (443 KB) |  | HTML iconHTML  

    We characterized the distribution of trap states in silicon-on-insulator (SOI) layers in epitaxial layer transfer (ELTRAN) wafers and in low-dose separation by implanted oxygen (SIMOX) wafers. We measured the front- and back-gate characteristics of MOSFETs with SOI layers of different thicknesses. We used the current-Terman method to estimate the trap states at the gate oxide (GOX)/SOI interface and at the SOI/buried oxide (BOX) interface separately. As a result, we concluded that the high-density trap states in the SOI layers in SIMOX wafers cause a gate-voltage shift, which is attributed to the charged trap states only in the inversion layer. We also found that the trap states are distributed within about 30 nm from the SOI/BOX interface in the SOI layer in SIMOX wafers, which indicates that the distribution of trap states originates from the oxygen implantation that is peculiar to the SIMOX process. View full abstract»

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  • Improving the Retention and Endurance Characteristics of Charge-Trapping Memory by Using Double Quantum Barriers

    Publication Year: 2008 , Page(s): 1708 - 1713
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (405 KB) |  | HTML iconHTML  

    We have studied the performance of double-quantum-barrier [TaN-Ir3Si]-[HfAlO-LaAlO3]-Hf0.3N0.2O0.5-[HfAlO-SiO2]-Si charge-trapping memory devices. These devices display good characteristics in terms of their plusmn9-V program/erase (P/E) voltage, 100-mus P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 degC. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced interface trap generation. View full abstract»

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  • On the Suitability of a High- k Gate Dielectric in Nanoscale FinFET CMOS Technology

    Publication Year: 2008 , Page(s): 1714 - 1719
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    The impact of a high-k gate dielectric on the device and circuit performances of nanoscale double-gate (DG) FinFET CMOS technology is examined via physics-based device/circuit simulations. DG FinFETs are designed with high k at the high- performance 45-nm node of the 2005 Semiconductor Industry Association International Technology Roadmap for Semiconductors (ITRS; Lg = 18 nm), and are compared with a pragmatic design in which the traditional SiON (or SiO2) gate dielectric is retained and kept relatively thick to avoid excessive gate tunneling current. Whereas it is presumed that a high-k dielectric, if and when adequately integrated, will significantly enhance CMOS scalability and performance, we show that there are heretofore unacknowledged compromising effects associated with it that undermine this enhancement. In fact, our results show that for DG FinFET CMOS, a high-k gate dielectric actually undermines speed performance while giving little improvement in scalability relative to the pragmatic design, whereas the latter can be scaled, with good performance, to the end of the ITRS. View full abstract»

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  • A Fully Three-Dimensional Atomistic Quantum Mechanical Study on Random Dopant-Induced Effects in 25-nm MOSFETs

    Publication Year: 2008 , Page(s): 1720 - 1726
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (618 KB) |  | HTML iconHTML  

    A fully 3-D atomistic quantum mechanical simulation is presented to study the random dopant-induced effects in nanometer metal-oxide-semiconductor field-effect transistors. The empirical pseudopotential is used to represent the single particle Hamiltonian, and the linear combination of bulk band method is used to solve the million atom Schrodinger equation. The gate threshold fluctuation and lowering due to the discrete dopant configurations are studied. It is found that quantum mechanical effects increase the threshold fluctuation while decreasing the threshold lowering. The increase of threshold fluctuation is in agreement with the researchers' early study based on an approximated density gradient approach. However, the decrease in threshold lowering is in contrast with the density gradient calculations. View full abstract»

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  • Ultralow Temperature Processing and Integration of Dielectric Resonators on Silicon Substrates for System-on-Chip Applications

    Publication Year: 2008 , Page(s): 1727 - 1732
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB) |  | HTML iconHTML  

    Ultralow temperature processing of Ba2Ti9O20 thin-film ceramics and the attachment of a porous dielectric resonator cylinder on a conducting prepatterned silicon substrate have been accomplished using a hydrothermal process at 150degC/3 h. Enhanced densification and mechanical strength at the bulk ceramic-thin-film interface were induced by a dissolution-crystallization process involving a sol-gel solution under 13-15 atm pressure. Recrystallization forms electrical bridges between powder particles to form an interconnected microstructure, which eliminates grain boundary defects and, hence, improves the dielectric properties. This method has potential for growth of dielectric resonators on integrated circuits for system-on-chip applications and is implemented for the fabrication of an integrated dielectric resonator antenna. View full abstract»

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  • Investigation of Thermal Crosstalk Between SOI FETs by the Subthreshold Sensing Technique

    Publication Year: 2008 , Page(s): 1733 - 1740
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1143 KB) |  | HTML iconHTML  

    Experimental-modeling investigation of the transient thermal crosstalk between the field-effect transistors implemented on a silicon-on-insulator substrate is reported. The measurements were performed using a high-speed electrical pulse-probe sampling technique, which allowed detection of thermally modulated subthreshold currents. The technique achieved a temperature resolution of ~50 mK, a time resolution of 5 ns, and a temperature sensitivity of ~0.6 muA/K. The finite-element method was used to solve the heat diffusion equation and to obtain the temperature profiles for the given device structures. The combined high-resolution experimental-simulation approach allowed the study of the thermal crosstalk between two adjacent devices and probe the local temperature at different locations of the structure. The effects of the interface quality, layer thickness, material selection, and interdevice spacing on the heat diffusion and device performance were investigated in detail. View full abstract»

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  • Numerical Study of Flicker Noise in p-Type  \hbox {Si}_{0.7}\hbox {Ge}_{0.3}/\hbox {Si} Heterostructure MOSFETs

    Publication Year: 2008 , Page(s): 1741 - 1748
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1012 KB) |  | HTML iconHTML  

    Device-level simulation capabilities have been developed to investigate low-frequency noise behavior in p-type Si0.7Ge0.3/Si heterostructure MOS (SiGe p-HMOS) transistors. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation, a layer-dependent correlated mobility fluctuation, and a Hooge mobility fluctuation in the buried and parasitic surface channels, respectively. Simulations based on such models have been conducted for SiGe p-HMOS transistors, and the results have been carefully correlated with experimental data. Quantitative agreement has been obtained in terms of the noise level dependence on gate biases, drain currents, and body biases, revealing the important role of the dual channels in the low-frequency noise behavior of SiGe p-HMOS devices. View full abstract»

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  • Double-Epilayer Structure for Low Drain Voltage Rating n-Channel Power Trench MOSFET Devices

    Publication Year: 2008 , Page(s): 1749 - 1755
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (721 KB) |  | HTML iconHTML  

    Double-epilayer structures were studied for n-channel low-voltage power trench MOSFET devices with drain-to-source voltage (Vds) of 20 V, and various device performance improvements have been observed. The threshold voltage variation (sigmaVth) can be reduced by increasing the intrinsic epilayer thickness. A 9% effective electron mobility mun improvement has been observed and is attributed to the reduced background phosphorus scattering. A Qgd of 3.1 nC for double- epilayer structure is observed which is about 30% lower than the 4.5 nC for the single-epilayer structure. This improved Qgd is due to both an increasing depletion width at the bottom of the trench and the well junction moving toward the trench bottom for the double-epilayer structure. The dependence of Qgd on the double-epilayer structure (intrinsic epilayer thickness and the doped epilayer resistivity) is found following the power law Qgd prop alphaX-b, where a and b are double-epilayer structure dependent. Compared to the single-epilayer structure, a double- epilayer structure can handle larger reverse current, suggesting a smaller basis resistance (Rbb') for the double-epilayer structure. This improvement ranges from 7% to 24% depending on the die pitch. A 20% less temperature dependence of device on-resistance for the double-epilayer structure has also been observed. This enables a large forward current capability, although the mechanism is not well understood. View full abstract»

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  • New High-Voltage ( > 1200 V) MOSFET With the Charge Trenches on Partial SOI

    Publication Year: 2008 , Page(s): 1756 - 1761
    Cited by:  Papers (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (936 KB) |  | HTML iconHTML  

    A novel silicon-on-insulator (SOI) high-voltage MOSFET structure and its breakdown mechanism are presented in this paper. The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI). Inversion charges located in the trenches enhance the electric field of the buried layer in the high-voltage blocking state, and a silicon window makes the depletion region spread into the substrate. Both of them modulate the electric field in the drift region; therefore, the breakdown voltage (BV) for a TPSOI LDMOS is greatly enhanced. Moreover, the Si window alleviates the self-heating effect. The influences of the structure parameters on device characteristics are analyzed for the proposed device structure. The TPSOI LDMOS with BV > 1200 V and the buried-layer electric field of EI > 700 V/ mum is obtained by the simulation on a 2-mum-thick SOI layer over 2-mum-thick buried oxide layer, and its maximal temperature reduces by 19 and 8.7 K in comparison with the conventional SOI and partial SOI devices. View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego