# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

## Filter Results

Displaying Results 1 - 21 of 21

Publication Year: 2008, Page(s):C1 - C2
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

Publication Year: 2008, Page(s): C2
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• ### A Survey of Automated Techniques for Formal Software Verification

Publication Year: 2008, Page(s):1165 - 1178
Cited by:  Papers (70)
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The quality and the correctness of software are often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific flaws. This paper surveys algorithms that perform automatic static analysis of software to detect programming errors or prove their absence. The three techniques considered are static analysis with abstract domains, mo... View full abstract»

• ### An Integrated Layout-Synthesis Approach for Analog ICs

Publication Year: 2008, Page(s):1179 - 1189
Cited by:  Papers (56)  |  Patents (1)
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In analog integrated circuit design, iterations between electrical and physical syntheses to counterbalance layout-induced performance degradations should be avoided as much as possible. One possible solution involves the integration of traditionally separated electrical and physical synthesis phases by including layout-induced effects right into the electrical synthesis phase in what has been cal... View full abstract»

• ### Logic Minimization and Testability of 2-SPP Networks

Publication Year: 2008, Page(s):1190 - 1202
Cited by:  Papers (13)
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The 2-SPP networks are three-level EXOR-AND-OR forms, with EXOR gates being restricted to fan-in 2. This paper presents a heuristic algorithm for the synthesis of these networks in a form that is fully testable in the stuck-at fault model (SAFM). The algorithm extends the EXPAND-IRREDUNDANT-REDUCE paradigm of ESPRESSO in heuristic mode, and it iterates local minimization and reshape of a solution ... View full abstract»

• ### DDBDD: Delay-Driven BDD Synthesis for FPGAs

Publication Year: 2008, Page(s):1203 - 1213
Cited by:  Papers (2)
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In this paper, we target field-programmable gate array (FPGA) performance optimization using a novel binary decision diagram (BDD)-based synthesis paradigm. Most previous works have focused on BDD size reduction during logic synthesis. In this paper, we concentrate on delay reduction and conclude that there is a large optimization margin through BDD synthesis for FPGA performance optimization. Our... View full abstract»

• ### Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled $RLC$ Interconnect Lines

Publication Year: 2008, Page(s):1214 - 1227
Cited by:  Papers (15)
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Analytical compact-form models for the signal transients and crosstalk noise of inductive-effect-prominent multicoupled lines are developed. Capacitive and inductive coupling effects are investigated and formulated in terms of the effective single-transmission-line model and effective transmission line parameters for fundamental switching modes. Arbitrary switching multicoupled lines are readily d... View full abstract»

• ### NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints

Publication Year: 2008, Page(s):1228 - 1240
Cited by:  Papers (84)
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In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor and the multilevel framework. To handle preplaced blocks, we use a two-stage smoothing technique, i.e., Gaussia... View full abstract»

• ### Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion

Publication Year: 2008, Page(s):1241 - 1252
Cited by:  Papers (20)
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Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source-shallow trench isolation (STI)-has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that combines detailed placement and active-layer fill insertion to exploit STI stress for performanc... View full abstract»

• ### Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations

Publication Year: 2008, Page(s):1253 - 1263
Cited by:  Papers (20)
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This paper solves the variation-aware decoupling capacitance (decap) budgeting problem. Unlike previous works which only consider worst case design, for the first time, we consider the input of both process variation and operation variation for decap budgeting. A novel stochastic current model is proposed that efficiently and accurately captures temporal correlation between clock cycles, logic-ind... View full abstract»

• ### Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study

Publication Year: 2008, Page(s):1264 - 1277
Cited by:  Papers (7)
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This paper presents a novel stochastic modeling and optimization framework for energy minimization in multicore systems running real-time applications with tolerance to deadline misses. This framework is based on stochastic application models, which capture the variability of and the spatial and temporal correlations among the workloads of concurrent and interdependent tasks that constitute the ap... View full abstract»

• ### Low-Power Test Data Application in EDT Environment Through Decompressor Freeze

Publication Year: 2008, Page(s):1278 - 1290
Cited by:  Papers (18)  |  Patents (4)
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This paper presents a new low-power test scheme integrated with the embedded deterministic test environment. The key contribution of this paper is a flexible test cube encoding scheme, which, in conjunction with a continuous flow decompressor, allows one to significantly reduce toggling rates when test patterns are fed into scan chains. The proposed solution requires neither additional design for ... View full abstract»

• ### A Linear-Time Approach for Static Timing Analysis Covering All Process Corners

Publication Year: 2008, Page(s):1291 - 1304
Cited by:  Papers (8)
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Manufacturing process variations lead to circuit timing variability and a corresponding timing yield loss. Traditional corner analysis consists of checking all process corners (combinations of process parameter extremes) to make sure that circuit timing constraints are met at all corners, typically by running static timing analysis (STA) at every corner. This approach is becoming too expensive due... View full abstract»

• ### Analyzing Functional Coverage in Bounded Model Checking

Publication Year: 2008, Page(s):1305 - 1314
Cited by:  Papers (14)
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Formal verification is an important issue in circuit and system design. In this context, bounded model checking (BMC) is one of the most successful techniques. However, even if all the specified properties can be verified, it is difficult to determine whether they cover the complete functional behavior of a design. We propose a practical approach to analyze coverage in BMC. The approach can easily... View full abstract»

• ### Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip

Publication Year: 2008, Page(s):1315 - 1328
Cited by:  Papers (11)
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The verification of system-on-chip is challenging due to its high level of integration. Multiple components in a system can behave concurrently and compete for resources. Hence, for simulation-based verification, we need a methodology that allows one to automatically generate test cases for testing concurrent and resource-competing behaviors. We introduce the use of a transfer-resource graph (TRG)... View full abstract»

• ### On Acceleration of SAT-Based ATPG for Industrial Designs

Publication Year: 2008, Page(s):1329 - 1333
Cited by:  Papers (59)
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Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for automatic test pattern generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on conjunctive normal forms (CNFs), the problem has to be transformed. During transformation... View full abstract»

• ### Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability

Publication Year: 2008, Page(s):1333 - 1338
Cited by:  Papers (24)
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A new statistical test data compression method that is suitable for IP cores of an unknown structure with multiple scan chains is proposed in this paper. Huffman, which is a well-known fixed-to-variable code, is used in this paper as a variable-to-variable code. The precomputed test set of a core is partitioned into variable-length blocks, which are, then, compressed by an efficient Huffman-based ... View full abstract»

• ### State-Sensitive X-Filling Scheme for Scan Capture Power Reduction

Publication Year: 2008, Page(s):1338 - 1343
Cited by:  Papers (10)  |  Patents (3)
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Based on the operation of a state machine, this paper elucidates a comprehensive frame for probability-based primary-input-dominated X-filling methods to minimize the total weighted switching activity (WSA) during the scan capture operation. Experimental results demonstrate that the proposed approach significantly reduces both average and peak WSAs. View full abstract»

• ### A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification

Publication Year: 2008, Page(s):1343 - 1347
Cited by:  Papers (1)
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This paper presents a compositional method with failure-preserving abstraction for scalable asynchronous design verification. It combines efficient state-space reductions and novel interface refinement and can dramatically reduce the complexity of state space while decreasing the introduction of false failures. This allows much larger designs to be verified as demonstrated in the experimental resu... View full abstract»

• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

Publication Year: 2008, Page(s): 1348
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

Publication Year: 2008, Page(s): C3
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## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu