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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 7 • Date July 2008

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Table of contents

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

A Survey of Automated Techniques for Formal Software Verification

An Integrated Layout-Synthesis Approach for Analog ICs

Logic Minimization and Testability of 2-SPP Networks

DDBDD: Delay-Driven BDD Synthesis for FPGAs

Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled $RLC$ Interconnect Lines

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints

Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion

Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations

Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study

Low-Power Test Data Application in EDT Environment Through Decompressor Freeze

A Linear-Time Approach for Static Timing Analysis Covering All Process Corners

Analyzing Functional Coverage in Bounded Model Checking

Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip

On Acceleration of SAT-Based ATPG for Industrial Designs

Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability

State-Sensitive X-Filling Scheme for Scan Capture Power Reduction

A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification

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