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IEEE Design & Test of Computers

Issue 3 • May-June 2008

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Displaying Results 1 - 25 of 29
  • [Front cover]

    Publication Year: 2008, Page(s): c1
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  • IEEE Computer Society Digital Library [advertisement]

    Publication Year: 2008, Page(s): c2
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  • Build Your Career in Computing [advertisement]

    Publication Year: 2008, Page(s): 201
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  • Table of contents

    Publication Year: 2008, Page(s):202 - 203
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  • Effective silicon debug is key for time to money

    Publication Year: 2008, Page(s): 204
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  • [Masthead]

    Publication Year: 2008, Page(s): 205
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  • Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis

    Publication Year: 2008, Page(s):206 - 207
    Cited by:  Papers (1)
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  • Functional Debug Techniques for Embedded Systems

    Publication Year: 2008, Page(s):208 - 215
    Cited by:  Papers (21)  |  Patents (71)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB) | HTML iconHTML

    Some problems in a new chip design or its embedded software show up only when a silicon prototype of the chip is placed in its intended target environment and the embedded software is executed. Traditionally, embedded-system debug is very difficult and time-consuming because of the intrinsic lack of internal system observability in the target environment. Design for debug (DFD) is the act of addin... View full abstract»

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  • In-System Silicon Validation and Debug

    Publication Year: 2008, Page(s):216 - 223
    Cited by:  Papers (37)  |  Patents (71)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (852 KB) | HTML iconHTML

    Silicon validation - proving a chip works correctly at speed and in system under different operating conditions - is always necessary, even for a "perfect" design. Silicon debug - finding the root cause of a malfunction - is necessary whenever a design is not flawless. First-silicon validation and debug require a labor-intensive engineering effort of several months and have become the least predic... View full abstract»

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  • Case Study on Speed Failure Causes in a Microprocessor

    Publication Year: 2008, Page(s):224 - 230
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (626 KB) | HTML iconHTML

    In this article, we identify the underlying speed paths and perform a detailed analysis on the effects of multiple input switching, cross-coupling noise, and localized voltage drop on microprocessor. We employ cycle-wise clock shrinks on a tester combined with a CAD methodology to unintrusively identify and analyze these speed paths. Understanding the causes of speed failures can help designers ma... View full abstract»

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  • IEEE Computer Society Information

    Publication Year: 2008, Page(s): 231
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  • Linking Statistical Learning to Diagnosis

    Publication Year: 2008, Page(s):232 - 239
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (719 KB) | HTML iconHTML

    As device and interconnect feature sizes shrink, silicon chip behavior becomes more sensitive to process and environmental variations and uncertainties. During the design phase, many effects of these variations are not explicitly or accurately modeled and simulated, either because doing so is too expensive or because the designer is not aware that a particular effect can significantly alter chip t... View full abstract»

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  • Survey of Scan Chain Diagnosis

    Publication Year: 2008, Page(s):240 - 248
    Cited by:  Papers (23)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (502 KB) | HTML iconHTML

    Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. The Achilles heel in the application of scan-based testing is the integrity of the scan chains. The amount of die area consumed by scan elements, chain connections, and control circuitry varies with different designs. Typically, each scan cell in a scan chain has an index number. The c... View full abstract»

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  • Advertisers' index

    Publication Year: 2008, Page(s): 249
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  • Physical Techniques for Chip-Backside IC Debug in Nanotechnologies

    Publication Year: 2008, Page(s):250 - 257
    Cited by:  Papers (11)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (642 KB) | HTML iconHTML

    Physical failure analysis remains indispensable for final defect confirmation, but is increasingly difficult due to semiconductor technology advances with smaller feature sizes, many metal layers, and flip-chip packaging. This article reports on how, despite an uphill battle, constant innovations keep physical failure analysis going. View full abstract»

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  • Overview of Debug Standardization Activities

    Publication Year: 2008, Page(s):258 - 267
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (984 KB) | HTML iconHTML

    The semiconductor industry is disaggregated, with a complex web of suppliers and consumers. Standards help to facilitate and simplify the debug process. This article provides an overview of current standardization activity. One area in need of such standardization is that of on-chip debug processes and instruments. The debug area particularly exhibits limited commonality between different IP provi... View full abstract»

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  • IEEE Computer Society Membership

    Publication Year: 2008, Page(s): 268
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  • IEEE Computer Society Membership and Subscriptions form

    Publication Year: 2008, Page(s):269 - 270
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  • IEEE Distributed Systems Online [advertisement]

    Publication Year: 2008, Page(s): 271
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  • Thousand-Core Chips [Roundtable]

    Publication Year: 2008, Page(s):272 - 278
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (402 KB) | HTML iconHTML

    The 2007 Design Automation Conference (DAC) had a special session entitled "1000 Core Chips," which was organized by Radu Marculescu (Carnegie Mellon University) and Li-Shiuan Peh (Princeton University). This session examined some of the ramifications of multicore chip design from four perspectives: technology, architecture, programming, and design automation. In this roundtable, held immediately ... View full abstract»

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  • IEEE Pervasive Computing [advertisement]

    Publication Year: 2008, Page(s): 279
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  • DATC Newsletter

    Publication Year: 2008, Page(s): 280
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  • IEEE Software 2008 Editorial Calendar

    Publication Year: 2008, Page(s): 281
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  • CEDA Currents

    Publication Year: 2008, Page(s):282 - 283
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  • Learning to assert yourself [review of Creating Assertion-Based IP (H.D. Foster and A.C. Krolnik; 2008)]

    Publication Year: 2008, Page(s):284 - 285
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty