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Electron Devices, IEEE Transactions on

Issue 6 • Date June 2008

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Displaying Results 1 - 25 of 48
  • Table of contents

    Page(s): C1 - 1274
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    Freely Available from IEEE
  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (51 KB)  
    Freely Available from IEEE
  • What is in a page charge?

    Page(s): 1275
    Save to Project icon | Request Permissions | PDF file iconPDF (37 KB)  
    Freely Available from IEEE
  • On Common–Base Avalanche Instabilities in SiGe HBTs

    Page(s): 1276 - 1285
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (996 KB) |  | HTML iconHTML  

    This paper presents a detailed investigation of the key device-level factors that contribute to the bias-dependent features observed in common-base (CB) dc instability characteristics of advanced SiGe HBTs. Parameters that are relevant to CB avalanche instabilities are identified, extracted from measured data, and carefully analyzed to yield improved physical insight, a straightforward estimation methodology, and a practical approach to quantify and compare CB avalanche instabilities. The results presented support our simple theory and show that CB-instability characteristics are strongly correlated with the parasitic base and emitter resistances. The influence of weak quasi-pinch-in effects are shown to contribute additional complexity to the bias dependence of the CB-instability threshold. Measured data from several technology nodes, including next-generation (300-GHz) SiGe HBTs, are presented and compared. Experimental analysis comparing different device geometries and layouts shows that while device size plays an important role in CB avalanche instabilities across bias, these parameters are not sensitive to standard transistor layout variations. However, novel measurements on emitter-ring tetrode transistor structures demonstrate the influence of perimeter-to-area ratio on CB stability and highlight opportunities for novel transistor layouts to increase . View full abstract»

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  • Bandstructure Effects in Silicon Nanowire Electron Transport

    Page(s): 1286 - 1297
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1171 KB) |  | HTML iconHTML  

    Bandstructure effects in the electronic transport of strongly quantized silicon nanowire field-effect-transistors (FET) in various transport orientations are examined. A 10-band sp3d5s* semiempirical atomistic tight-binding model coupled to a self-consistent Poisson solver is used for the dispersion calculation. A semi-classical, ballistic FET model is used to evaluate the current-voltage characteristics. It is found that the total gate capacitance is degraded from the oxide capacitance value by 30% for wires in all the considered transport orientations ([100], [110], [111]). Different wire directions primarily influence the carrier velocities, which mainly determine the relative performance differences, while the total charge difference is weakly affected. The velocities depend on the effective mass and degeneracy of the dispersions. The [110] and secondly the [100] oriented 3 nm thick nanowires examined, indicate the best ON-current performance compared to [111] wires. The dispersion features are strong functions of quantization. Effects such as valley splitting can lift the degeneracies particularly for wires with cross section sides below 3 nm. The effective masses also change significantly with quantization, and change differently for different transport orientations. For the cases of [100] and [111] wires the masses increase with quantization, however, in the [110] case, the mass decreases. The mass variations can be explained from the non-parabolicities and anisotropies that reside in the first Brillouin zone of silicon. View full abstract»

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  • Screening Effects Between Field-Enhancing Patterned Carbon Nanotubes: A Numerical Study

    Page(s): 1298 - 1305
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (373 KB) |  | HTML iconHTML  

    A numerical investigation of the topographic field-enhancement factor for structures including individual vertically aligned carbon nanotubes (VACNTs) and arrays of VACNT is presented. Some previously reported results for simple structures are reviewed first. Then, the extent of the zones of field enhancement and significant screening effects surrounding a given structure is discussed. The investigation with combined VACNT confirms the criterion that the spacing between identical CNT should be about twice their height to minimize screening effects. This statement is generalized to structures having different height ratios. The possibility of combining patterns of different height VACNT to minimize screening effects while allowing a larger surface density of such emitters is then investigated. The results show that height anisotropies in VACNT arrays can significantly reduce the field-emission current for a given applied field. A subsequent study that takes into account Joule heating and radiation losses during field emission demonstrates that, for height anisotropies larger than 5%, the VACNT tips reach temperatures above the onset temperature for selective field-assisted evaporation. This phenomenon occurs before the field-emission current from the nonideal films matches the targeted current value deduced from ideal VACNT arrays. View full abstract»

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  • Modeling Thermal Effects in Nanodevices

    Page(s): 1306 - 1316
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1520 KB) |  | HTML iconHTML  

    In order to investigate the role of self-heating effects on the electrical characteristics of nanoscale devices, we implemented a 2D Monte Carlo device simulator that includes the self-consistent solution of the energy balance equations for both acoustic and optical phonons. The acoustic and optical phonon temperatures are fed back into the electron transport solver through temperature-dependent scattering tables. The electrothermal device simulator was used in the study of different generations of nanoscale fully depleted silicon-on-insulator devices that are either already in production or will be fabricated in the next five to ten years. We find less degradation due to self-heating in very short channel device structures due to the increasing role of nonstationary velocity-overshoot effects which are less sensitive to the local temperature. View full abstract»

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  • Computationally Efficient Physics-Based Compact CNTFET Model for Circuit Design

    Page(s): 1317 - 1327
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1076 KB) |  | HTML iconHTML  

    We present a computationally efficient physics-based compact model designed for the conventional CNTFET featuring a MOSFET-like operation. A large part of its novelty lies on the implementation of a new analytical model of the channel charge. In addition, Boltzmann Monte Carlo (MC) simulation is performed with the challenge to cross-link this simulation technique to the compact modeling formulation. The comparison of the electrical characteristics obtained from the MC simulation and from the compact modeling demonstrates the compact model accuracy within its range of validity. Then, from a study of the CNT diameter dispersion for three technological processes, the compact model allows us to determine the CNTFET threshold voltage distribution and to evaluate the resulting dispersion of the propagation delay from the simulation of a ring oscillator. View full abstract»

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  • Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects

    Page(s): 1328 - 1337
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (987 KB) |  | HTML iconHTML  

    Metallic carbon nanotubes (CNTs) have received much attention for their unique characteristics as a possible alternative to Cu interconnects in future ICs. Until this date, while almost all fabrication efforts have been directed toward multiwalled CNT (MWCNT) interconnects, there is a lack of MWCNT modeling work. This paper presents, for the first time, a detailed investigation of MWCNT-based interconnect performance. A compact equivalent circuit model of MWCNTs is presented for the first time, and the performance of MWCNT interconnects is evaluated and compared against traditional Cu interconnects, as well as Single-Walled CNT (SWCNT)-based interconnects, at different interconnect levels (local, intermediate, and global) for future technology nodes. It is shown that at the intermediate and global levels, MWCNT interconnects can achieve smaller signal delay than that of Cu interconnects, and the improvements become more significant with technology scaling and increasing wire lengths. At 1000- global or 500- intermediate level interconnects, the delay of MWCNT interconnects can reach as low as 15% of Cu interconnect delay. It is also shown that in order for SWCNT bundles to outperform MWCNT interconnects, dense and high metallic-fraction SWCNT bundles are necessary. On the other hand, since MWCNTs are easier to fabricate with less concern about the chirality and density control, they can be attractive for immediate use as horizontal wires in VLSI, including local, intermediate, and global level interconnects. View full abstract»

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  • Driving Characteristics of a High-Efficacy AC PDP With an Auxiliary Electrode

    Page(s): 1338 - 1344
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (981 KB) |  | HTML iconHTML  

    A new driving waveform was proposed in order to stabilize the driving characteristics of a high-efficacy AC plasma-display panel (PDP) with a coplanar gap of 200 mum and an auxiliary electrode. To stabilize the reset and address discharge, an erase pulse was applied to the auxiliary electrode instead of the sustain electrode after the sustain period. The write pulse was applied to the scan electrode, and a reset discharge was induced between the scan and auxiliary electrodes. As a result, the minimum address voltage could be reduced to a level similar to that achieved with a conventional ac PDP with a coplanar gap of 80 mum. Furthermore, the address-discharge time lag of the ac PDP with a coplanar gap of 200 mum was improved to a level that is comparable with that of the ac PDP with a coplanar gap of 80 mum. View full abstract»

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  • Prevention of Boundary Image Sticking in an AC Plasma Display Panel Using a Vacuum Sealing Process

    Page(s): 1345 - 1351
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1262 KB) |  | HTML iconHTML  

    Boundary image sticking can be inherently prevented in an ac plasma display panel fabricated using a vacuum sealing process. The results indicate that residual impurities, such as nitrogen or oxygen, are essentially related to the production of boundary image sticking. When checking the production of boundary image sticking in a test panel fabricated using a or an flow during the vacuum sealing process, no boundary image sticking appeared in the case of a flow, whereas boundary image sticking was produced with an flow, although the test panel was fabricated using a vacuum sealing process. Consequently, reducing the residual impurity, particularly oxygen, based on a vacuum sealing process can inherently prevent boundary image sticking. View full abstract»

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  • New Observation of Mobility and Reliability Dependence on Mechanical Film Stress in Strained Silicon CMOSFETs

    Page(s): 1352 - 1358
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1068 KB) |  | HTML iconHTML  

    This paper shows that dc device performance and reliability characteristics of CMOSFETs do not have the same dependence on the film stress of contact etch stopping layers (CESLs) in strained silicon technology. Two kinds of CESLs, namely, plasma-enhanced chemical vapor deposition (PE-CVD) SiN and low-pressure CVD SiON, with tensile and compressive stresses, respectively, were used to induce channel stress. To further analyze the effects of stress, the film stress of PE-CVD SiN was intentionally split into compressive stress and tensile stress. It is shown that the initial Dit of NMOS with a tensile stress film is less than that with a compressive stress, whereas in the case of PMOS, compressive stress demonstrated less Dit than the tensile-stress film. However, device degradation by hot and cold carriers is heightened more by tensile stress than by compressive stress for both NMOS and PMOS. Therefore, the compressive stress is desirable to improve hot-carrier immunity in NMOSFETs, whereas the tensile stress is necessary to improve the dc device performance. Hence, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress engineering of nanoscale CMOSFETs. View full abstract»

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  • Characteristic Instabilities in HfAlO Metal–Insulator–Metal Capacitors Under Constant-Voltage Stress

    Page(s): 1359 - 1365
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (571 KB) |  | HTML iconHTML  

    Time-dependent characteristic changes of metal-insulator-metal (MIM) capacitors with HfAlO dielectric prepared by atomic-layer deposition under constant-voltage stress (CVS) were studied. It was found that relative dielectric constant , dielectric loss , temperature coefficient of capacitance , and frequency coefficient of capacitance gradually increase during CVS testing, whereas the voltage dependence of capacitance weakens. It was also found that changes in -value, , and during CVS testing linearly depend on changes in . These three linear relationships are basically explained by a dielectric-response model proposed for a ldquoflat-lossrdquo dielectric. That is, the increases in -value, , and are attributed to the dielectric-loss increase caused by voltage stress. Stress-time dependence of the dielectric-loss increase is expressed very well by a power function. That is, the power exponent obtained by a curve fitting linearly increases with stress voltage and decreases with increasing aluminum concentration in the HfAlO dielectric. This result indicates that aluminum addition into the HfAlO dielectric can improve the characteristic stabilities of a MIM capacitor under voltage stress. View full abstract»

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  • Lateral Nonuniformity Effects of Border Traps on the Characteristics of Metal–Oxide–Semiconductor Field-Effect Transistors Subjected to High-Field Stresses

    Page(s): 1366 - 1372
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (338 KB) |  | HTML iconHTML  

    The lateral nonuniformity (LNU) effects of border traps are studied by exploring both the high- and low-frequency characteristics in N-type channel metal-oxide-semiconductor field-effect transistors. According to experimental data, the deterioration of nonuniformity is significantly enhanced at low frequencies. The cause may be due to the additional trapped charges of border traps (near-interface oxide traps) under the low-frequency measurement. This model is successfully simulated by the combination of low-frequency C-V curves with the heavily and lightly damaged regions. Additionally, the double-peak charge-pumping current is observed in low-frequency measurements, which can further support our hypothesis that border-trap-enhanced LNU exists. Finally, the geometric effect of the polygate and the thickness effect of the gate oxide are also investigated for the nonuniformity issue. View full abstract»

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  • Avalanche Breakdown Due to 3-D Effects in the Impact-Ionization MOS (I-MOS) on SOI: Reliability Issues

    Page(s): 1373 - 1378
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    In this paper, we report on reliability issues concerning the impact-ionization MOS (I-MOS). For the first time, the anomalously high off current in the planar I-MOS is studied owing to light-emission experiments. We show that a first breakdown occurs at the width borders of the device, followed by the theoretical volume breakdown. This result is intensively studied through 3D TCAD simulations. The results are correlated with electrical measurements. We finally propose and validate a degradation mechanism based on charge trapping. View full abstract»

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  • Effects of Oxynitride Buffer Layer on the Electrical Characteristics of Poly-Silicon TFTs Using \hbox {Pr}_{2}\hbox {O}_{3} Gate Dielectric

    Page(s): 1379 - 1385
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1008 KB) |  | HTML iconHTML  

    In this paper, we have developed high-k Pr2O3 poly-Si thin-film transistors (TFTs) using different N2O plasma power treatments. High-k Pr2O3 poly-Si TFT devices using a 200-W plasma power exhibited better electrical characteristics in terms of high effective carrier mobility, high driving current, small subthreshold slope, and high ION/IOFF current ratio. This result is attributed to the smooth Pr2O3/poly-Si interface and low interface trap density. Pr2O3 poly-Si TFT with a 200-W N2O plasma power also enhanced electrical reliabilities such as hot carrier and positive bias temperature instability. All of these results suggest that a high-k Pr2O3 gate dielectric with the oxynitride buffer layer is a good candidate for high-performance low-temperature poly-Si TFTs. View full abstract»

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  • Analytical Electron-Mobility Model for Arbitrarily Stressed Silicon

    Page(s): 1386 - 1390
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (433 KB) |  | HTML iconHTML  

    It was experimentally and numerically indicated that both the valley splitting and effective-mass variation contribute to the stress-induced enhancement of electron mobility in the MOSFET channel. In this paper, an analytical electron-mobility model for arbitrarily strained silicon is presented. The electron-mobility model includes the strain effects of both the effective-mass variation and valley degeneration. The expression of strained conduction band used in the analytical model is based on the theory and accords well with numerical results of nonlocal empirical pseudopotential method (EPM). By using the mobility model, mobilities under different stresses are investigated. View full abstract»

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  • MOSFET Performance Scaling—Part I: Historical Trends

    Page(s): 1391 - 1400
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (493 KB) |  | HTML iconHTML  

    A simple analytical model that describes MOSFET operation in saturation from subthreshold to strong inversion is used to derive a new formulation of the intrinsic switching delay of the transistor. The proposed model follows the scaling trend of experimental ring-oscillator data better than the conventional CV/I metric. The historical trend of MOSFET performance scaling is examined, and it is shown that the continuous increase of the carrier velocity in the channel has been the main driver for the improved transistor performance with scaling. The dependence of velocity and mobility in recent strain-engineered devices is studied based on published experimental data, and a theory is proposed to justify this dependence. It is shown that the virtual-source velocity depends on low-field mobility more strongly than what was previously believed, in spite of the fact that state-of-the-art MOSFETs operate at 60%-65% of their ballistic limit. These observations will be used in Part II of this paper to explore the tradeoffs between key device parameters in order for the commensurate scaling of the device performance with its dimensional scaling to continue in the future high-performance CMOS generations. View full abstract»

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  • MOSFET Performance Scaling—Part II: Future Directions

    Page(s): 1401 - 1408
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (698 KB) |  | HTML iconHTML  

    The analytical MOSFET intrinsic delay introduced in Part I of this paper is used to examine the tradeoffs between key device elements required in order for the performance scaling trend to continue in future high-performance CMOS generations. A scaling scenario based on contacted source/drain gate pitch is presented and used to examine the prospects of MOSFET performance in the future nodes. It is shown that, from 32-nm node onwards, MOSFET performance will counterscale, mainly due to increase in the parasitic gate capacitance as a result of proximity of the gate and source/drain electrodes. As a case study, the dependence of the transistor performance on various device parameters at the 32-nm node is analyzed. Reducing the fringing capacitance is shown to be the most effective approach to meet the required transistor delay. View full abstract»

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  • ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers

    Page(s): 1409 - 1416
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1499 KB) |  | HTML iconHTML  

    Considering gate-oxide reliability, a new electrostatic discharge (ESD) protection scheme with an on-chip ESD bus (ESD_BUS) and a high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage N- and P-type MOS devices that can be safely operated under the 2.5-V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (positive-to-VSS, negative-to-VSS, positive-to-VDD, and negative-to-VDD) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13-mum CMOS process have confirmed that the proposed new ESD protection scheme has high human-body model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low- voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces. View full abstract»

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  • Comparison of MONOS Memory Device Integrity When Using \hbox {Hf}_{1 - x - y}\hbox {N}_{x}\hbox {O}_{y} Trapping Layers With Different N Compositions

    Page(s): 1417 - 1423
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (435 KB) |  | HTML iconHTML  

    We have studied the nitrogen composition dependence of the characteristics of Hf1-x-yNxOy/SiO2/Si MONOS memory devices. By increasing the N composition in the Hf1-x-yNxOy trapping layer, both the memory window and high-temperature retention improved. The Hf0.3N0.2O0.5 MONOS device displayed good characteristics in terms of its plusmn9-V program/erase (P/E) voltage, 100-mus P/E speed, large initial 2.8-V memory window, and a ten-year extrapolated retention of 1.8 V at 85degC or 1.5 V at 125degC. View full abstract»

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  • A PSP-Based Small-Signal MOSFET Model for Both Quasi-Static and Nonquasi-Static Operations

    Page(s): 1424 - 1432
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (369 KB) |  | HTML iconHTML  

    In this paper, a small-signal MOSFET model is described, which takes the local effects of both velocity saturation and transverse mobility reduction into account. The model is based on the PSP model and is valid for both quasi-static and nonquasi-static (NQS) operations. Recently, it has been found that, in the presence of velocity saturation, the low-frequency capacitances cannot be determined from the Ward-Dutton charge-partitioning scheme. By use of the small-signal model developed in this paper, it is demonstrated that, in the presence of velocity saturation, no terminal drain and source charges exist, from which the capacitances can be derived. The small-signal model enables the determination of the correct capacitive behavior in the presence of velocity saturation. Furthermore, it is demonstrated how the small-signal model can be used to determine the number of collocation points needed in the large-signal NQS PSP model. Finally, inclusion of the local variation of mobility reduction due to the vertical electrical fields provides insight into the approach commonly applied in compact modeling, where these fields are replaced by global ones depending on the terminal voltages only. View full abstract»

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  • An Evaluation of the CMOS Technology Roadmap From the Point of View of Variability, Interconnects, and Power Dissipation

    Page(s): 1433 - 1440
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB) |  | HTML iconHTML  

    In this paper, using the new generation of model for assessment of CMOS technologies and roadmaps software, we discuss the CMOS logic roadmap in terms of circuit performance, power dissipation, and variability, such as loaded ring-oscillator delay, as well as through 6T-SRAM functionality. It is shown that these criteria will have to be taken into account in addition to the traditional 17%-per-year delay improvement to construct a new industrially viable roadmap. View full abstract»

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  • A Quasi-Two-Dimensional Compact Drain–Current Model for Undoped Symmetric Double-Gate MOSFETs Including Short-Channel Effects

    Page(s): 1441 - 1448
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (515 KB) |  | HTML iconHTML  

    A drain-current model for undoped symmetric double-gate MOSFETs is proposed. Channel-length modulation and drain-induced barrier lowering are modeled by using an approximate solution of the 2D Poisson equation. The new model is valid and continuous in linear and saturation regimes, as well as in weak and strong inversions. Excellent agreement was found with Silvaco-ATLAS simulations. View full abstract»

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  • Discrete Dopant Fluctuations in 20-nm/15-nm-Gate Planar CMOS

    Page(s): 1449 - 1455
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1229 KB) |  | HTML iconHTML  

    We experimentally quantified, for the first time, the random dopant distribution (RDD)-induced threshold voltage standard deviation up to 40 mV for 20-nm-gate planar complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Discrete dopants have been statistically positioned in the 3-D channel region to examine the associated carrier transportation characteristics, concurrently capturing ldquodopant concentration variationrdquo and ldquodopant position fluctuation.rdquo As the gate length further scales down to 15 nm, the newly developed discrete dopant scheme features an effective solution to suppress the 3-sigma-edge single-digit dopant-induced variation by the gate work function modulation. The results of this paper may postpone the scaling limit projected for planar CMOS. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology